A Simulation Study on the Impact of InP Barrier on InGaAs/InP Hetero Junction Gate all around MOSFET

Abstract:

In this work, we have analyzed the digital and analog performance for InGaAs/InP heterojunction Gate all around MOS structure. A detailed study on the impact of Barrier thickness on different analog and digital performance for an InGaAs/InP hetero structure GAA MOSFET is carried out by using TCAD device simulation. The electrical parameters such as surface potential, electric field, transfer characteristics, output characteristics, transconductance and output conductance is carried out and analyzed by varying the barrier thickness from 1 nm to 4 nm. Based on the simulation results it is investigated that the effect of the all electrical parameters in the nanoscale devices. It has been seen from the presented results that the influence of barrier thickness variation gives the notable improvement in drain current. The impact of InGaAs/InP hetero structure and barrier thickness variation claims GAA MOSFET as a promising candidate for VLSI applications. Keywords: Heterojunction, InGaAs/InP, TCAD, Analog parameters.

• Periodical: Journal of Nano Research (Volume 60)
• Pages: 113-123
• DOI: https://doi.org/10.4028/www.scientific.net/JNanoR.60.113
• Online since: November 2019
• Authors: P. Vimala*, T.S. Arun Samuel
• Keywords: Drain Current, Electric Field, Heterojunction, InGaAs/InP, Surface Potential, TCAD, TFET

References

[1] X. Li, Y. Cao, D.C. Hall, P. Fay, B. Han,A. Wibowo, N. Pan , GaAs MOSFET using InAlP native oxide as gate dielectric,, IEEE Electron Device Letters, Year: 2004, Volume: 25, Issue: 12.

DOI: 10.1109/led.2004.838555

[2] B. Cheng,A. R. Brown,S. Roy,A. Asenov, PBTI/NBTI-Related Variability in TB-SOI and DG MOSFETs,, IEEE Electron Device Letters ,Year: 2010, Volume: 31 , Issue: 5 ,Pages: 408 – 410.

DOI: 10.1109/led.2010.2043812

[3] Md. Rokib Hasan, Muniyat Siddiqui Rafa, Marwan Hossain, Farah Rafia,Maisha Rashid Nidhi, Gate Length Engineering Impact of Sub-10 nm GaN-Based DG-MOSFETs,,2017 IEEE International WIE Conference on Electrical and Computer Engineering (WIECON-ECE), Year: 2017, Pages: 117 – 120.

DOI: 10.1109/wiecon-ece.2017.8468884

[4] Md. Rokib Hasan, Influence of device performance of Sub-10 nm GaN-based DG-MOSFETs over conventional Si-based SG-MOSFETs,,2017 4th International Conference on Advances in Electrical Engineering (ICAEE) Year: 2017, Pages: 697 – 702.

DOI: 10.1109/icaee.2017.8255445

[5] Matthias Passlack,Ravi Droopad,Peter Fejes,Lingquan Wang , Electrical Properties of GaO\GaAs Interfaces and GdGaO Dielectrics in GaAs-Based MOSFETs,, IEEE Electron Device Letters ,Year: 2009 Volume: 30 , Issue: 1 Pages: 2 – 4.

DOI: 10.1109/led.2008.2007579

[6] Y. Cao, X. Li, J. Zhang, P. Fay, T.H. Kosel, D.C. Hall, Microwave performance of GaAs MOSFET with wet thermally oxidized InAlP gate dielectric,, IEEE Electron Device Letters, Year: 2006 Volume: 27, Issue: 5, Pages: 317 – 319.

DOI: 10.1109/led.2006.872898

[7] Jae Young Song, Woo Young Choi, Ju Hee Park, Jong Duk Lee, Byung Gook Park, Design optimization of gate-all-around (GAA) MOSFETs,, IEEE Transactions on Nanotechnology, Year: 2006, Volume: 5 , Issue: 3, Pages: 186 – 191.

DOI: 10.1109/tnano.2006.869952

[8] K. Rajagopalan, R. Droopad, J. Abrokwah, P. Zurcher, P. Fejes, M. Passlack, 1-μm Enhancement Mode GaAs N-Channel MOSFETs With Transconductance Exceeding 250 mS/mm, , IEEE Electron Device Letters, Year: 2007, Volume: 28, Issue: 2, Pages: 100 – 102.

DOI: 10.1109/led.2006.889502

[9] P. Vimala and N.R. Nithin Kumar, Analytical Quantum Model for Germanium Channel Gate-All-Around (GAA) MOSFET,, Journal of Nano Research, Year:2019, Volume: 59, Pages: 137-148.

DOI: 10.4028/www.scientific.net/jnanor.59.137

[10] Yi Song, Chen Zhang, Ryan Dowdy, Kelson Chabak, Parsian K. Mohseni, Wonsik Choi, Xiuling Li, III-V Junctionless Gate-All-Around Nanowire MOSFETs for High Linearity Low Power Applications, , IEEE Electron Device Letters ,Year: 2014 Volume: 35 ,Issue: 3 Pages: 324 – 326.

DOI: 10.1109/led.2013.2296556

[11] P.Vimala, Balamurugan, N.B, A Compact Quantum Model for Cylindrical Surrounding Gate MOSFETs using High-k Dielectrics,, Journal of Electrical Engineering and Technology, Year 2014, Volume 9, Issue 2,pages 649-654.

DOI: 10.5370/jeet.2014.9.2.649

[12] N. Seoane, G. Indalecio, E. Comesana, A. J. Garcia Loureiro, M. Aldegunde,K. Kalna, Three-dimensional simulations of random dopant and metal-gate workfunction variability in an In0.53Ga0.47As GAA MOSFET,, IEEE Electron Device Letters,Year: 2013, Volume: 34 , Issue: 2, Pages: 205 – 207.

DOI: 10.1109/led.2012.2230313

[13] Kalyan Biswas, Angsuman Sarkar, Chandan Kumar Sarkar, Impact of barrier thickness on Analog, RF and Linearity performance of nanoscale DG heterostructure MOSFET,,Superlattices and Microstructures, Volume 86, October 2015, Pages 95-104.

DOI: 10.1016/j.spmi.2015.06.047

[14] P.Vimala and N. B. Balamurugan, Modeling and simulation of centroid and inversion charge density in cylindrical surrounding gate MOSFETs including quantum effects,, Journal of Semiconductors, Year 2013,Volume 34, Issue 11.

DOI: 10.1088/1674-4926/34/11/114001

[15] SilvacoATLAS: Device simulation software. Silvaco Int, Santa Clara (2012).

[16] Raseong Kim; Uygar E. Avci; Ian A. Young, Source/Drain Doping Effects and Performance Analysis of Ballistic III-V n-MOSFETs,, IEEE Journal of the Electron Devices Society, 2015, Vol. 3, no. 1.p.37 – 43.

DOI: 10.1109/jeds.2014.2363389

[17] Yi Cui Xiang feng Duan Jiang tao Hu Charles M. Lieber, Doping and Electrical Transport in Silicon Nanowires,, The Journal of Physical Chemistry B, 2000, vol.104, no. 22, pp.5213-5216.

DOI: 10.1021/jp0009305