Solder Joint Reliability Analysis of WLCSP Based on Inelastic Analysis

Article Preview

Abstract:

Nonlinear finite element analysis is performed to evaluate the reliability of the solder joint of wafer level chip scale package (WLCSP) under accelerated temperature cycling test. The solder joint is subjected to the inelastic strain that is generated during the temperature cycling test due to the thermal expansion mismatch between the various materials of the package and PCB (printed circuit board). The equivalent stress, equivalent inelastic strain, total shear strain, and hysteresis loop of the solder joint are determined in the simulation. The equivalent inelastic strain and total shear strain range of the joint are obtained as damage criterion to predict the solder fatigue. Both Coffin-Manson and Modified Coffin-Manson fatigue life prediction models are used to estimate the thermal fatigue life of WLCSP solder joints under temperature cycling test. Also, the effects of the material properties of the stress buffer layer (SBL) on the fatigue life of the solder joint are discussed.

You might also be interested in these eBooks

Info:

Periodical:

Key Engineering Materials (Volumes 306-308)

Pages:

643-648

Citation:

Online since:

March 2006

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2006 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

[1] Darveaux, R., Effect of Simulation Methodology on Solder Joint Crack Growth Correlation, Proc 50th Electronic Components and Technology Conference, pp.1048-1058, (2000).

DOI: 10.1109/ectc.2000.853299

Google Scholar

[2] Zahn, B. A., Impact of Ball Via Configuration on Solder Joint Reliability in Tape-Based, Chip-Scale Packages, Proc 52 nd Electronic Components and Technology Conference, pp.1475-1483, (2002).

DOI: 10.1109/ectc.2002.1008301

Google Scholar

[3] Lau, J. H., Lee, S. R. and Chang C., Solder Joint Reliability of Wafer Level Chip Scale Packages (WLCSP): A Time-Temperature-Dependent Creep Analysis, , Journal of Electronic Packaging, Vol. 122, pp.311-316, (2000).

DOI: 10.1115/1.1289769

Google Scholar

[4] Zhao, X. J., Zhang, G. O., Gaers, J. F. J. M., and Ernst, L. J., Solder Fatigue Prediction Using Interfacial Boundary Volume Criterion, Journal of Electronic Packaging, Vol. 125, pp.582-588, (2003).

DOI: 10.1115/1.1604160

Google Scholar

[5] Engelmaieii, W., Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 6, No. 3, pp.52-57, (1983).

DOI: 10.1109/tchmt.1983.1136183

Google Scholar