Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems
Power-efficient multipliers are essential for micro systems, where low-power signal processing hardware is demanded. This paper presents an adiabatic array multiplier based on PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. It is composed of a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-lookahead adder. For comparison, a conventional array multiplier is also implemented. Full-custom layouts are drawn, and HSPICE simulations are carried out using the net-list extracted from their layout. The adiabatic and conventional array multipliers have been embedded in a test chip, which have been fabricated with Chartered 0.35um process and tested to verify its function.
J. P. Hu et al., "Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems", Key Engineering Materials, Vols. 460-461, pp. 473-478, 2011