Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems

Jian Ping Hu; Xiao Ying Yu; Bin Bin Liu

doi:10.4028/www.scientific.net/KEM.460-461.473

Paper Titles

Analysis of Intrusion Detection System
p.451

The Research of Exact Orthogonal Nonseparable Four-Variate Wavelet Pack Bases with Finite Support
p.455

Development of On-Line Performance Monitoring and Fault Diagnosis System for Diesel Generator System
p.461

Design and Manufacture of Energy-Recycling Pads for Low-Power Chips
p.467

Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems
p.473

A Self-Adaptive Model of Two-Level for Dynamic Peer-to-Peer Networks
p.479

Face Detection Using PSO Algorithm
p.485

Bioremediation of Aquiculture Wastewater by Microalgae Isochrysis zhanjiangensis and Production of the Biomass Material
p.491

Optimization and Analysis Emulation System of the Controlled Mechanism Based on Windows
p.496

HomeKey Engineering MaterialsKey Engineering Materials Vols. 460-461Manufacturing and Testing of Adiabatic Array...

Manufacturing and Testing of Adiabatic Array Multiplier for Micro Power Digital Systems

Abstract:

Power-efficient multipliers are essential for micro systems, where low-power signal processing hardware is demanded. This paper presents an adiabatic array multiplier based on PAL-2N (pass-transistor adiabatic logic with NMOS pull-down configuration) circuits. It is composed of a multiplier array containing partial product generators and 1-bit (half and full) adders, and a final carry-lookahead adder. For comparison, a conventional array multiplier is also implemented. Full-custom layouts are drawn, and HSPICE simulations are carried out using the net-list extracted from their layout. The adiabatic and conventional array multipliers have been embedded in a test chip, which have been fabricated with Chartered 0.35um process and tested to verify its function.