Physical Implementation and Manufacture of Adiabatic Flip-Flops for Micro Power Systems

Abstract:

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Flip-flops are main logic cells in digital systems, thus power-efficient designs are essential for micro systems, where ultra low-power hardware is demanded. This paper presents physical implementation and manufacture of adiabatic flip-flops based on CPAL (Complementary Pass-transistor Adiabatic Logic) circuits. The two mode-10 adiabatic counters based on four-phase and two-phase CPAL circuits have been implemented. For comparison, a conventional mode-10 counter using static CMOS circuits has also been embedded in a test chip. Full-custom layouts are drawn, and full parasitic extraction is done. The post-layout simulations are carried out using HSPICE. The chip has been fabricated with Chartered 0.35um process and tested.

Info:

Periodical:

Key Engineering Materials (Volumes 460-461)

Edited by:

Yanwen Wu

Pages:

724-729

DOI:

10.4028/www.scientific.net/KEM.460-461.724

Citation:

H. Li et al., "Physical Implementation and Manufacture of Adiabatic Flip-Flops for Micro Power Systems", Key Engineering Materials, Vols. 460-461, pp. 724-729, 2011

Online since:

January 2011

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Price:

$35.00

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