Analysis of Stress-Strain Hysteresis Loop and Prediction of Thermal Fatigue Life for Chip Size Package Solder Joints

Ikuo Shohji; Tatsuya Kobayashi; Tomotake Tohei

doi:10.4028/www.scientific.net/KEM.462-463.76

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HomeKey Engineering MaterialsKey Engineering Materials Vols. 462-463Analysis of Stress-Strain Hysteresis Loop and...

Analysis of Stress-Strain Hysteresis Loop and Prediction of Thermal Fatigue Life for Chip Size Package Solder Joints

Abstract:

The aim of this study is to investigate the relationship between the inelastic strain range and the thermal fatigue lives of chip size package solder joints with Sn-Pb and Sn-Ag-Cu solder balls. The inelastic strain range was examined by finite element analysis. In both solder joints, the exponential terms in the inelastic strain range term in the Coffin-Manson equation were evaluated as 1.8 - 2.3. These values are very close to the conventional one used in Sn-Pb and the Pb containing solders. The inelastic strain range is almost proportional to the temperature range in the Sn-Pb solder joint. On the contrary, the inelastic strain range is proportional to approximately the square root of the temperature range in the Sn-Ag-Cu solder joint. The deference depends on the change of the stress-strain hysteresis curve in the thermal cycle.

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Periodical:

Key Engineering Materials (Volumes 462-463)

Pages:

76-81

DOI:

https://doi.org/10.4028/www.scientific.net/KEM.462-463.76

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Online since:

January 2011

Authors:

Ikuo Shohji, Tatsuya Kobayashi, Tomotake Tohei

Keywords:

Chip Size Package, Coffin-Manson Equation, Finite Element Analysis (FEA), Sn-Ag-Cu, Sn-Pb, Solder, Thermal Fatigue Life

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