Design and Implementation of the RF Front-End All-Digital Phase-Locked Loop in the UHF RFID Reader
PLL is an important part of the RF front-end module,its performance is directly related to stability and accuracy of the RF base-band signal extracted. A FPGA-based all-digital PLL is implemented in this thesis, Hilbert digital phase detector (HDPD) ,Numerically controlled oscillator (NCO) and FIR digital loop filter module implemented using Verilog language ensure accuracy and stability to Sample input Baseband signal modulated. The experiments confirmed that the all-digital PLL designed in this thesis can overcome the defects of DPLL based on semi-analog circuits; and has high Operating frequency, exact capture time, precision adjustable, simple interface, and so on; can be widely used in radio frequency identification (RFID) and automatic control system.
Y. L. Wang et al., "Design and Implementation of the RF Front-End All-Digital Phase-Locked Loop in the UHF RFID Reader", Key Engineering Materials, Vols. 474-476, pp. 63-68, 2011