The Use of Computer Simulation in the Electronic Packaging Process

Boleslav Psota; Martin Buršík; Ivan Szendiuch

doi:10.4028/www.scientific.net/KEM.592-593.201

Paper Titles

Evaluation of Three-Point Bending Fracture Tests of Concrete Specimens with Polypropylene Fibres via Double-K Model
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Fracture-Micromechanics Based Model of Mortars Susceptible to Shrinkage
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Crack Growth Modelling in the Silicon Nitride Ceramics by Application of the Cohesive Zone Approach
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Temperature Field and Solidification Structure of a Ductile-Cast-Iron Roller
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The Use of Computer Simulation in the Electronic Packaging Process
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Numerical Simulation of Damage to Fracture Transition in Metals Based on the Statistical Model of Mesodefect Evolution
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Application of Multi-Parameter Fracture Mechanics to Study of Crack Propagation Angle in Selected Mixed-Mode Geometry
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Numerical Model of Plate from Hollow Core Panels with Contact – Target Pairs
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A Numerical Estimation of Fatigue Crack Tip Plastic Zone Size and Shape under Mixed-Mode Loading Condition
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HomeKey Engineering MaterialsKey Engineering Materials Vols. 592-593The Use of Computer Simulation in the Electronic...

The Use of Computer Simulation in the Electronic Packaging Process

Abstract:

This paper deals with the use of the computer simulation for semiconductor chip attach investigation, where the wire bonding is the mostly used process. The main focus lays on the correct definition of the capillary trace, which is essential for creation of a good bond contact as for chip, as well for package or substrate pad. Several simulations for different shapes of loops were created and compared with real bonds, which were done based on the settings from the analysis.

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Periodical:

Key Engineering Materials (Volumes 592-593)

Pages:

201-204

DOI:

https://doi.org/10.4028/www.scientific.net/KEM.592-593.201

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Cite this paper

Online since:

November 2013

Authors:

Boleslav Psota*, Martin Buršík, Ivan Szendiuch

Keywords:

ANSYS Workbench , Chip Connection, Simulation, Wirebonding

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References

[1] M. BURŠÍK, M. NOVOTNÝ, J. JANKOVSKÝ, E. HEJÁTKOVÁ, I. SZENDIUCH, Testing and Simulation of Wire Bonding Attach for higher Current. In Electronics System Integration Technology Conference ESTC 2010 in Berlin. 1. Berlin, Germany: 2010, pp.1-4.

DOI: 10.1109/estc.2010.5642805

Google Scholar

[2] Wire Bonding or Wirebonding Process. Www. SiliconFarEast. com - All About Semiconductor Manufacturing [online]. [cit. 2012-04-08]. Web: http: /www. siliconfareast. com/wirebond. htm.

Google Scholar

[3] M. BURŠÍK, E. HEJÁTKOVÁ. Pouzdření a propojování mikroelektronických struktur. In: MMTE –practical guide for lab exercises [online]. 2012 [cit. 2013-04-29]. Web: https: /www. vutbr. cz/elearning/course/view. php?id=124545.

Google Scholar

[4] G. HARMAN: Wire Bonding in Microelectronics, McGraw Hill Companies, New York, 2010, ISBN 978-0-07-170101-3.

Google Scholar