Advanced 3D Packaging of Chips and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks

Christoph Sander; Martin Gall; Kong Boon Yeap; Ehrenfried Zschech

doi:10.4028/www.scientific.net/KEM.592-593.563

Paper Titles

Monitoring of the Damage in Stone Blocks by Means of Non-Destructive Methods
p.545

Detection of Inhomogeneities and Cracks in Composite Materials by the Method of Partial Discharges
p.549

Study of Initial Stages of Fatigue Process Using Non-Destructive Testing Methods
p.553

Microstructural Investigations of Nickel-Based Superalloys with Different Structure
p.557

Advanced 3D Packaging of Chips and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks
p.563

Fracture of Irradiated Austenitic Stainless Steel with Special Reference to Irradiation Assisted Stress Corrosion Cracking
p.569

The Effect of Radiation-Induced Structural Changes under Accelerated Irradiation on the Behavior of Water-Cooled Reactor Pressure Vessel Steels
p.573

Intergranular Embrittlement of Nuclear Reactor Pressure Vessel Steels
p.577

Influence of Morphology of Deformation Induced α´-Martensite on Stress-Strain Response in a Two Phase Austenitic-Martensitic-Steel
p.582

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Advanced 3D Packaging of Chips and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks

Abstract:

Managing the emerging internal mechanical stress in chips particularly if they are 3D-tscked is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology/flow emerges. This physics-based simulation, however, requires materials parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. Therefore, effective composite-type materials data for several regions of interest are needed. Advanced techniques to measure FEA-and design-relevant properties such as local and effective Youngs modulus and effective CTE values were developed and described in this paper. These data show a clear orientation dependence, caused by the chip design.