Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA

Vidas Abraitis; Žydrūnas Tamoševičius

doi:10.4028/www.scientific.net/SSP.144.214

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Control of Mobile Crane by Means of Fuzzy Logic Controller
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Managing Changes in Product Configurations
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Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA
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Infrared Reflective Coatings for Window Glazing
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Determination of Factors Affecting Safety Stress in Machine Design by Using Artificial Intelligence Technologies
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Modeling of Trainer's Electric Drive Control
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Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA

Abstract:

Transition delay testing of sequential circuits in a clocked environment is analyzed. There are presented two test pattern generator methods for built in self testing of the circuit implemented as Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR) structures are used for test sequence generation. The circuits are tested as the black boxes under Transition fault model. Experimental results of the test pattern generation methods are presented and analyzed. Results compared with exhaustive test of transition faults for ASICs and programmable integrated circuits with given configuration.