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Online since: August 2013
Authors: Jun Yang, Hong Hui Deng, Rui Zhang, Yong Sheng Yin
References
[1] Ahmed M A A,Christopher D,Robert S,et al.A 14-bit 125MS/s IF/RF sampling pipelined ADC with 100dB SFDR and 50 fs jitter.IEEE J Solid-State Circuits,2006,27(8) :1846
[2] Luo Lei, Xu Jun and Ren Junyan.A High-Performance Sample-and-Hold Circuit with Sampling Bandwith Compensation.Journal of Semiconductors,2008,29(6) :1122
[3] Ion E.Opris, Laurence D.Lewicki and Bill C.Wong.