A 100-MS/s CMOS Sample-and-Hold Circuit with Input Common Mode Feedback

Jun Yang; Hong Hui Deng; Rui Zhang; Yong Sheng Yin

doi:10.4028/www.scientific.net/AMR.748.847

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 748A 100-MS/s CMOS Sample-and-Hold Circuit with Input...

A 100-MS/s CMOS Sample-and-Hold Circuit with Input Common Mode Feedback

Abstract:

A high performance sample-and-hold (S/H) circuit with input common mode feedback (ICMFB) is presented. The ICMFB is used to ensure that the input common mode voltage for the sample-and-hold amplifier (SHA) is maintained at a known value during the hold phase of operation in order to reduce the differential output error when the sample capacitor and feedback capacitor has mismatch. Meanwhile, bootstrapped switches are used to lower the switch on-resistance and reduce the effect of switch non-idealities. Then a low power two stage high gain wideband SHA is designed to guarantee the holding accuracy. Hspice simulated results based on SMIC 0.13μm 1P5M CMOS process under 1.2V supply voltage shows a 108.4 dB spurious free dynamic range (SFDR) at Nyquist input @Fs=100MS/s. The designed S/H circuit has been used in the front end of 14-bit 100MS/s Pipelined ADC adapted for single-ended applications.

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Periodical:

Advanced Materials Research (Volume 748)

Pages:

847-852

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.748.847

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Online since:

August 2013

Authors:

Jun Yang, Hong Hui Deng, Rui Zhang, Yong Sheng Yin

Keywords:

Bootstrapped Switch, Input Common Mode Feedback, S/H Circuit, SFDR, SHA

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References

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