Incremental Circuit and Sensitivity Simulations Using Iterated Timing Analysis Algorithm

Chun Jung Chen; Yu Wei Chen; Chang Lung Tsai; Chih Jen Lee; Jenn Dong Sun

doi:10.4028/www.scientific.net/AMR.748.839

Paper Titles

With DGPS-RTK Terminal Yard Cranes Real-Time Operating System
p.815

Temperature Controller of Heating Furnace Based on Fuzzy Neural Network Technology
p.820

Design of Direct Digital Synthesizer Based on FPGA
p.829

A Dual-Mode MPPT Algorithm Based on the Golden Section Point of the PV System
p.833

Incremental Circuit and Sensitivity Simulations Using Iterated Timing Analysis Algorithm
p.839

A Study for Embedded Software Double-Fault Testability
p.843

A 100-MS/s CMOS Sample-and-Hold Circuit with Input Common Mode Feedback
p.847

Design of the High-Speed High-Resolution Latched Comparator
p.853

Design of a Novel Excitation Circuit for Low Perming Error Fluxgate
p.859

HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 748Incremental Circuit and Sensitivity Simulations...

Incremental Circuit and Sensitivity Simulations Using Iterated Timing Analysis Algorithm

Abstract:

This paper investigates incremental circuit/sensitivity simulations for large-scale MOSFET circuits using the well-known ITA (Iterated Timing Analysis) algorithm. Incremental simulation uses the result waveforms of previous simulation to fasten the simulation speed, which is quite advantageous in the practical incremental-modifying circuit design strategy. Most proposed methods have been implemented and tested to justify their advantages.

You might also be interested in these eBooks

Material and Manufacturing Technology IV

View Preview

Info:

Periodical:

Advanced Materials Research (Volume 748)

Pages:

839-842

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.748.839

Citation:

Cite this paper

Online since:

August 2013

Authors:

Chun Jung Chen, Yu Wei Chen, Chang Lung Tsai, Chih Jen Lee, Jenn Dong Sun

Keywords:

Circuit Simulation, Incremental Simulation, Iterated Timing Analysis, Relaxation-Based Algorithms, Transient Sensitivity Computation

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

References

[1] C. J. Chen, Incremental Circuit Simulation and Simulation-on-demand based on Backward-traversing Waveform Relaxation and Portion-simulating Algorithms, 2010 3rd International Conference on Computational Intelligence and Industrial Application, Wuhan, China, December 4-5, (2010).

DOI: 10.1016/j.phpro.2012.05.310

Google Scholar

[2] Y. C. Ju, and R.A. Saleh, Incremental circuit simulation using waveform relaxation, Proceeding of the ACM/IEEE DAC, pp.8-11, (1992).

DOI: 10.1109/dac.1992.227872

Google Scholar

[3] R. A. Saleh and A. R. Newton, The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation, IEEE Trans., Computer-aided Design, vol. 8, pp.1286-1298, December (1989).

DOI: 10.1109/43.44509

Google Scholar

[4] C. J. Chen, W. S. Feng, Relaxation-based transient sensitivity computations for MOSFET circuits, IEEE Trans. on Computer-aided Design, Vol. 14, No. 2, pp.173-185, Feb. (1995).

DOI: 10.1109/43.370426

Google Scholar