Design of the High-Speed High-Resolution Latched Comparator

Abstract:

Based on the latch and comparison theory, a high-speed high-resolution latched comparator is designed in this paper by using a standard 0.18μm/1.8V CMOS process. With the sampling frequency of 400MHz, the Cadence Spectre simulation results show that the regeneration time is around 230ps and only 11.83mV offset voltage, power consumption is 2.12mW, the minimum voltage resolution is 0.2mV without any input offset error. The circuit is applicable for the design of a high-speed high-resolution A/D converter.

• Periodical: Advanced Materials Research (Volume 748)
• Pages: 853-858
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.748.853
• Online since: August 2013
• Authors: Ye Wang, Yong Sheng Yin, Lang Wang, Hong Hui Deng
• Keywords: A/D Converter, Latch Comparator, Low Voltage, Positive Feedback

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