Design of SDH Positive/Zero/Negative Justification Circuits Based on FPGA

Zhou Juan Cui; Liao Lin Hu

doi:10.4028/www.scientific.net/AMR.748.874

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 748Design of SDH Positive/Zero/Negative Justification...

Design of SDH Positive/Zero/Negative Justification Circuits Based on FPGA

Abstract:

A successful design which used FPGA to do Positive/Zero/Negative Justification for adapting E1 (2.048Mbit/s) to SDH C-12 is presented. Gray code is adopted to realize the sampling of write pointer in reading clock domain and induct frequency doubling technology to deduct/insert reading clock, and a positioning counting device is set to complete the positioning insert of specified bytes. Asynchronous FIFO and Ping-Pong operation technique are both adopted. The design realizes stimulation, placement and routing under Quartus II 9.0 circumstances. It is a reusable hardware module which increases performance when compared to existing solutions.

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Periodical:

Advanced Materials Research (Volume 748)

Pages:

874-878

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.748.874

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Online since:

August 2013

Authors:

Zhou Juan Cui, Liao Lin Hu

Keywords:

Asynchronous FIFO, Field-Programmable Gate Array (FPGA), Positive/Zero/Negative Justification, SDH

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