Leakage Power Reduction in 32-bit Digital Comparator Using Modified Power Gating Technique

Abstract:

As scaling down of CMOS transistor’s channel length is done for miniaturization, the design community primarily focuses on the high performance & power-aware design. The power consumption of any circuit solely holds the performance and the life of it. But static power consumption deteriorates them and dominates the dynamic power consumption because of its leakage components. A modified approach of pulse triggering in the Power Gating technique called MPG (Modified Power Gating) is proposed to reduce the static power consumption (leakage power) of digital subsystems. Sub threshold leakage power of MPG Inverter (INV) and 32-bit Digital Comparator (DC) is analyzed and reduced with 35% to 40% leakage savings compared with conventional and existing techniques by simulating it in Cadence GPDK.

• Periodical: Applied Mechanics and Materials (Volume 742)
• Pages: 741-744
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.742.741
• Online since: March 2015
• Authors: G. Amuthavalli*, R. Gunasundari, A. Nijandan
• Keywords: 32-bit Digital Comparator, Cadence, Circuit-Level, Power Gating, Short Pulse, Static Power, Sub Threshold Leakage Power

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