Papers by Author: Akimasa Kinoshita

Abstract: SiC power module with low loss and high reliability was developed by utilizing IEMOSFET and SBD. The IEMOSFET is the SiC MOSFET with high channel mobility in which the channel region is the p-type carbon-face epitaxial layer with low acceptor concentration. Elemental technologies for the high channel mobility and the high reliability of the gate oxide have been developed to realize the excellent characteristics by the IEMOSFET. The SBD was designed so as to minimize the forward voltage drops and the reverse leakage current. For the fabrication of these SiC power devices, the mass production technology such as gate oxidation, ion implantation and following activation annealing have been also developed.

Abstract: The 1200V class silicon carbide Schottky barrier diodes were designed and fabricated. The drift layer resistance was reduced in order to realize low forward voltage drops. Since the low drift layer resistance led to the low breakdown voltage, the avalanche withstanding capability should be enhanced not to cause the destructive breakdown. By means of the optimized device design, we succeeded to realize the low forward voltage drop while maintaining the high avalanche withstanding capability. The forward voltage drops at 200A/cm² were 1.35V at 25°C and 1.63V at 175°C, respectively. The avalanche withstanding capability was more than 3500mJ/cm² at 25°C. By substituting SiC-SBDs for Si-pin diodes, the estimated total power loss of the module comprised by Si-IGBTs and the diodes was reduced by 35%. We could also confirm that no failures happened after long term reliability tests.

Abstract: It is known that a Schottky barrier height (b) of metal/C-face 4H-SiC Schottky barrier diode (SBD) differ from b of metal/Si-face 4H-SiC SBD. Furthermore, b of metal/4H-SiC SBD varies with annealing temperature. We fabricate 0.231mm2 SBD with Ti/SiC interface using Si-face and C-face 4H-SiC. These SBDs are annealed at several temperatures after a formation of the Ti/SiC interface. As a result, b of Ti/C-face 4H-SiC interface annealed at 400 oC is nearly equal to b of Ti/Si-face 4H-SiC interface annealed at 500 oC and the n-values of these SBDs are nearly equal to the ideal value (unity). Using that annealing condition, we fabricated 25mm2 junction barrier Schottky (JBS) diodes with Ti/SiC interface on Si-face and C-face 4H-SiC epitaxial substrate. b of Si-face and C-face JBS diodes are 1.26eV and 1.24eV, respectively. The leakage currents for both Si-face and C-face JBS diodes are less than 1mA/cm2. The current of 100A is obtained at the forward bias voltage of 1.95V and 2.16V for the Si-face JBS and the C-face JBS.

Abstract: The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.

Abstract: In this paper, we report a new polishing technique regarding the elimination of step bunching on the silicon carbide (SiC) surface. The step bunching generation is often observed as frequent phenomenon on the surface of SiC epilayers grown on low off-angle (0001) SiC wafers and on SiC devices after annealing to activate the dopants. We polished the step bunching surface using a chemical mechanical polishing (CMP) technique reported in a previous study, and we succeeded to improve the morphology with a flat and smooth surface which showed a small Rms value of around 0.1nm. We especially found an excellent polishing effect for the control of leakage current in reverse I-V characteristics of SiC Schottky barrier diodes (SBD).

Abstract: The Ti/4H-SiC Schottky barrier diodes with a field limiting ring (FLR) structure are fabricated. Two types of SBDs are prepared; one (SBD-A) is covered and another (SBD-B) isn’t covered with a carbon cap during high temperature annealing after ion implantation. The breakdown voltage at room temperature for SBD-A and SBD-B are 1400 V and 1000 V, respectively. The breakdown for both SBDs occurs due to an avalanche breakdown. The light emission images are obtained at the breakdown voltage by photo emission microscope (PEM). The light emission is observed along an FLR of the SBD-A as designed. On the other hand, the spot of light emission is observed on a FLR structure of the SBD-B. This light emission spot indicates that leakage current is concentrated because an electrical field concentration is generated at this one for the SBD-B. The root-mean-square roughness of the Al-implanted region on the FLR structure calculated from the atomic force microscopy (AFM) images for the SBD-A and the SBD-B are 0.697 nm and 5.58 nm, respectively. Therefore it is considered that large surface roughness on the FLR decreases breakdown voltage of SBD because an electrical field concentration is generated at a spot.

Abstract: The C(000-1) face of 4H-SiC has a lot of advantages for the power device fabrication such as the highest oxidation ratio and a smooth surface. However, the DMOS type power MOSFETs on the C(000-1) face have not been realized because of the difficulty of epitaxial growth and of high quality MOS interface formation. We have systematically investigated the device fabrication techniques for power MOSFETs on the C(000-1) face, and succeeded with the IEMOS which have blocking voltage of 660V and an on-resistance of 1.8mΩcm2 and excellent dynamic characteristics.

Abstract: The reaction and phase formation of the Ti/SiC Schottky contact as a function of the annealing temperature (400~700oC) were investigated. The Schottky barrier height (fb) and the crystal structure of the samples annealed at the different temperature were measured by the forward current-voltage (IV) characteristics and the x-ray diffraction (XRD), respectively. XRD measurements were performed in the w-2q scan and the pole figure measurement for Ti (101) diffraction peak. The fb was changed as a function of temperature. It was concluded that the fb variation and non-uniformity of the samples annealed at 400oC, 500oC, 600 oC and 700oC was caused by changing the condition at the interface between SiC substrate and Ti. We fabricated the 600V Ti/SiC silicidation SBD annealed at 500oC for 5min. As a result, a low forward voltage drop, low reverse leakage current and stability at high temperature (200 oC) for the Ti/SiC silicidation SBD were shown.

Abstract: Dislocations in a substrate wafer of 4H-SiC with an epi-layer were observed using technique of monochromatic synchrotron X-ray topography in a grazing incidence geometry. Six different Burgers vectors of basal plane dislocations and threading edge dislocations were identified by changing the Bragg reflections, and by analysis of images of dislocation. We identify some relations of the Burgers vector and the dislocation contrast observed for g=11 2 8. Some of these relationships are discussed in this report.

Abstract: 4H-SiC substrate wafers with epi-layers were observed using monochromatic synchrotron X-ray topography in grazing incidence geometries, to investigate the defects in the epi-layer. Misfit dislocations with b=+1/3[11 2 0] caused by the difference in lattice parameter between the epi-layer and the substrate were observed. The misfit dislocations are located near the interface as edge dislocations, and appear at the top surface as screw dislocations on basal planes. It was observed that more than half of them were introduced from the growing epi-layer surface. The misfit dislocations and some screw dislocations with b=+1/3[11 2 0] are observed to remain as basal plane dislocations at the surface, while other basal plane dislocations were converted to threading edge dislocations in the epi-layer.