Papers by Author: Anant K. Agarwal

Abstract: The last three years have seen a rapid growth of 600 V and 1200 V SiC Schottky diodes primarily in the Power Factor Correction (PFC) circuits. The next logical step is introduction of a SiC MOSFET to not only further improve the power density and efficiency of the PFC circuits but also to enable the entry of all SiC power modules in Pulse Width Modulated (PWM) based power converters such as motor control in 600-1200 V range. The combination of SiC MOSFET and Schottky diodes will offer 60-80% lower losses in most low voltage applications at normal operating temperatures (< 200°C) where no significant improvements in packaging are required. This will cover most commercial applications with the exception of those having to function under extreme environment (>200°C) such as applications in automotive, aerospace and oil/gas exploration. For these high temperature applications, a case can be made for 600 - 2000 V Bipolar Junction Transistors (BJTs) and PiN diodes provided we do our homework on high temperature packaging. A number of interesting device related problems persist in bipolar devices such as forward voltage increase in PiN diodes and current gain degradation in BJTs. For very high voltage (>10 kV) applications such as those found in utilities (Transmission and Distribution), Large Drives and Traction, a case can be made for >10 kV PiN diodes, IGBTs, Thyristors and GTOs. While IGBTs will be restricted to <200°C junction temperature, the PiN diodes, Thyristors and GTOs may be operated at >250°C junction temperature provided that the high temperature, high voltage packaging issues are also addressed. Significant progress has been made in the development of the p-channel IGBTs and GTOs. The main issues seem to be the VF degradation due to stacking fault formation and improvement of minority carrier life-time.

Abstract: We theoretically and experimentally compare the performance of a new JBS rectifier structure, the Buried Channel JBS (BC-JBS) rectifier, with that of the Lateral Channel JBS (LC-JBS) rectifier with 1.5kV blocking capability in 4H-SiC. The BC-JBS rectifier employs buried p-type regions to create a vertical JFET region to reduce the surface electric field at Schottky contact during reverse blocking while the LC-JBS rectifier adds a lateral channel together with the vertical JFET region to protect the surface Schottky interface during high-voltage blocking conditions. The LC-JBS rectifier offers low reverse leakage current while the BC-JBS rectifier demonstrates lower specific on-resistance. The optimized LC-JBS rectifiers show low forward drop (<1.8V) with PiN-like reverse characteristics.

Abstract: 4H-SiC PiN rectifiers with implanted anode and single-zone JTE were fabricated using AlN capped anneal. The surface damage during the high temperature activation anneal is significantly reduced by using AlN capped anneal. The forward drop of the PiN rectifiers at 100A/cm2 is 3.0V while the leakage current is less than 10-7A/cm2 up to 90% breakdown voltage at room temperature. With 6μm thick and 2×1016cm-3 doped drift layer, the PiN rectifiers can achieve near ideal breakdown voltage up to 1050V. Hole impact ionization rate was extracted and compared with previously reported results.

Abstract: Gate oxide reliability measurements of 4H-SiC DMOSFETs were performed using the Time Dependent Dielectric Breakdown (TDDB) technique at 175°C. The oxide lifetime is then plotted as a function of the electric field. The results show the projected oxide lifetime to be > 100 years at an operating field of ~3 MV/cm. Device reliability of 2.0 kV DMOSFETs was studied by stressing the gate with a constant gate voltage of +15 V at a temperature of 175°C, and monitoring the forward I-V characteristics and threshold voltage for device stability. Our very first measurements show very little variation between the pre-stress and post-stress conditions up to 1000 hrs of operation at 175°C. In addition, forward on-current stressing of the MOSFETs show the devices to be stable up to 1000 hrs of operation.

Abstract: 8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.

Abstract: For the first time, 4H-SiC RF bipolar junction transistors have been used to produce an output power in excess of 2.1 kW at 425 MHz. For an input pulse width of 2 μs and 1% duty cycle, the power gain at peak output power is 6.3 dB with the collector efficiency and power added efficiency [PAE] being 45% and 35%, respectively, at a collector supply voltage of 75 V in a class C configuration. The package consists of 24 cells (2 chips) having an emitter periphery of approximately 1 inch per cell. Each cell produced a DC current gain (β) of 15 and a common emitter breakdown voltage (BVCEO) greater than 250 V. A peak output power of 87 W per cell was obtained at 425 MHz, as compared to the earlier report of 50 W per cell [1, 2] by using a shorter pulse width and duty cycle.

Abstract: SiC BJTs show instability in the I-V characteristics after as little as 15 minutes of operation. The current gain reduces, the on-resistance in saturation increases, and the slope of the output characteristics in the active region increases. This degradation in the I-V characteristics continues with many hours of operation. It is speculated that this phenomenon is caused by the growth of stacking faults from certain basal plane dislocations within the base layer of the SiC BJT. Stacking fault growth within the base layer is observed by light emission imaging. The energy for this expansion of the stacking fault comes from the electron-hole recombination in the forward biased base-emitter junction. This results in reduction of the effective minority carrier lifetime, increasing the electron-hole recombination in the base in the immediate vicinity of the stacking fault, leading to a reduction in the current gain. It should be noted that this explanation is only a suggestion with no conclusive proof at this stage.

Abstract: This paper reports on a 400 watt boost converter using a SiC BJT and a SiC MOSFET as the switch and a 6 Amp and a 50 Amp SiC Schottky diode as the output rectifier. The converter was operated at 100 kHz with an input voltage of 200 volts DC and an output voltage of 400 volts DC. The efficiency was tested with an output loaded from 50 watts to 400 watts at baseplate temperatures of 25°C, 100°C, 150°C and 200°C. The results show the converter in all cases capable of operating at temperatures beyond the range possible with silicon power devices. While the converter efficiency was excellent in all cases, the SiC MOSFET and 6 Amp Schottky diode had the highest efficiency. Since the losses in a boost converter are dominated by the switching losses and the switching losses of the SiC devices are unaffected by temperature, the efficiency of the converter was effectively unchanged as a function of temperature.

Abstract: We report on the development of the first 1 cm x 1 cm SiC Thyristor chip capable of blocking 5 kV. This demonstrates the present quality of the SiC substrate and epitaxial material. A forward drop of 4.1 V at 100 A and 25°C has been measured. The turn-on delay is found to be a strong function of the gate current. At a gate current of 0.5 A, a turn-on delay of 250 ns is observed for an anode to cathode current of 200 A. The turn-on delay reduces to 72 ns for an IG = 1.5 A. The turn-on rise time is a strong function of the anode to cathode voltage, VAK. At VAK =230 V, the turn-on rise-time is 300 ns for IAK =200 A. The rise-time reduces to 26 ns for VAK = 500 V.