Papers by Author: Greg Dunne

Abstract: This paper highlights ongoing efforts to validate performance, reliability and robustness of GE SiC MOSFETs for Aerospace and Industrial applications. After summarizing ruggedness and reliability testing performed on 1.2kV MOSFETs, two application examples are highlighted. The first demonstrates the 1.2kV device performance in a prototype high frequency 75kW Aviation motor drive. The second highlights the experimental demonstration of a 99% efficient 1.0MW solar inverter using 1.7kV MOSFET modules in a two-level topology switching at 8kHz. Both applications illustrate that SiC advantage is not only in improved performance, but also in significant system cost savings through simplifications in topology, controls, cooling and filtering.

Abstract: This paper discusses SiC JTE design tradeoffs required to maximize device performance while minimizing consumed die area, fabrication cost and maintaining good reliability. Modeling and experimental results are provided.

Abstract: In this paper, we show state of the art, low on-resistance, 25mW/1.2kV and 43mW/2.5kV SiC MOSFETs with excellent design robustness and process control such that the parametric spread of key device characteristics are approaching Si products. The impact of starting material variability on device performance is shown and design sensitivity curves are presented.

Abstract: We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.

Abstract: Due to the Silicon Carbide (SiC) material’s high electric field strength, wide bandgap, and good thermal conductivity, 4H-SiC thyristors are attractive candidates for pulsed power applications. With a thinner blocking layer almost an order of magnitude smaller than its Silicon (Si) counterpart, these devices promise very fast turn-on capabilities as full conductivity modulation occurs >10 times faster than comparable silicon thyristors, low leakage currents at high junction temperatures and at high voltage, and much lower forward voltage drop at high pulse currents. Our progress on the development of large area (4mm x 4mm) SiC thyristors is presented in this paper.

Abstract: nversion layers of 4H and 6H Silicon carbide based MOS devices are characterized by Gated Hall measurements to determine the trap density close to the conduction band edge and the main scattering mechanisms that limit the mobility. MOS gated Hall structures were fabricated on 4H SiC polytype with p-type doping of 5X1015cm-3 and 2X1017cm-3. MOS Gated Hall structures were also fabricated on 6H SiC polytype with p-type doping of 7.5X1015cm-3. The gate oxide was grown thermally with N2O as a precursor followed by a NO post oxidation anneal. The inversion layer Hall mobility on the 6H SiC MOSFET sample decreased with increasing temperature from room temperature to 423K, while on the 4H SiC MOSFET samples the inversion layer mobility increased slowly. Approximately 50% of the total charge density at the interface of both 6H and 4H SiC MOSFETs was found to be trapped charge. The dominant scattering mechanism in 6H SiC MOSFETs was inferred to be phonon scattering based on the temperature dependence and theoretical estimates of the phonon limited mobility. In the case of 4H SiC, we infer that at surface roughness scattering is the dominant scattering mechanisms at high surface fields.

Abstract: Low channel mobility is one of the biggest challenges to commercializing SiC MOSFETs. Accurate mobility measurement is essential for understanding the mechanisms that lead to low mobility. The most widely used effective mobility measurements overestimate the inversion charge for devices that have high level of defects. Mobility measured by the Hall effect is more accurate; however the conventional Hall mobility measurement is tedious. In this work, we demonstrate a wafer-level Hall measurement technique, which is simple and convenient to implement. With this method, extensive study of the mobility degradation is possible.

Abstract: Reliability of the gate oxide on SiC is a pressing concern for deploying SiC MOS-based devices in real systems. While good projected oxide reliability was obtained recently under highly accelerated test conditions, indication that such projection may not be valid at lower operating fields was also reported. In this work, results from long-term TDDB stress (over 7 months) at 6 MV/cm and 300 °C on 4H-SiC MOS capacitors is reported. We confirm that lifetime projection from high-field data continues to be valid and no change in field acceleration factor is observed. The discrepancy between our results and the early prediction of poor reliability is examined.

Abstract: Silicon Carbide (SiC) based metal oxide semiconductor field effect transistors (MOSFETs) were fabricated and characterized using gated hall measurements with different p-type substrate doping concentration (7.2X1016cm-3 and 2X1017 cm-3). An interface trap state density of 5X1013 cm-2eV-1 was observed nearly 0.1 eV above the conduction band edge leading to the conclusion that these states are present in the silicon dioxide rather than the interface. The Hall mobility of the MOSFETs decreased from 26.5 to 20 cm2/Vs as the doping was increased from 7.2X1016 to 2X1017cm-3. The decrease in mobility is primarily due to an increase in the surface electric field that causes an increase in surface roughness scattering. The inversion layer mobility when plotted as a function of average surface electric field is not independent of doping concentration as is the case in silicon MOSFETs because the dominant scattering mechanism is not phonon scattering.

Abstract: SiC vertical MOSFETs were fabricated and characterized to achieve a blocking voltage of 950 Volts and a specific on-resistance of 8.4 mW-cm2. Extrapolations of time-dependent dielectric breakdown measurements versus applied electric field indicate that the gate oxide mean-time to failure is approximately 105 hours at 250°C.