Papers by Author: Joshua D. Caldwell

Abstract: Graphene, a 2D material, has motivated significant research in the study of its in-plane charge carrier transport in order to understand and exploit its unique physical and electrical properties. The vertical graphene-semiconductor system, however, also presents opportunities for unique devices, yet there have been few attempts to understand the properties of carrier transport through the graphene sheet into an underlying substrate. In this work, we investigate the epitaxial graphene/4H-SiC system, studying both p and n-type SiC substrates with varying doping levels in order to better understand this vertical heterojunction.

Abstract: Shockley stacking fault (SSF) contraction in 4H-SiC was investigated, in-situ, under varying temperature and ultraviolet (UV) intensity. Contraction of single SSFs at room temperature was observed for the first time under low power UV excitation of 0.04 W/cm². At temperatures above 150 °C, complete SSF contraction occurred for UV power at 0.2 W/cm². In contrast to expansion, SSF contraction occurred in discrete jumps between pinning sites along existing C-core partials. Luminescence from the pinning sites suggest they may be local concentrations of point defects. Additionally, a change in the line direction of the Si-core partials by ~25o off the direction was observed.

Abstract: Over the past decade, improvements in silicon carbide growth and materials has led to the development of commercialized unipolar devices such as Schottky diodes and MOSFETs, however, much work remains to realizing the goal of wide-scale commercialization of both unipolar and bipolar devices such as pin diodes or IGBTs, for high applications requiring high powers, operating in elevated temperatures or radiation environments or for many fast switching applications. Despite the great strides that have been made in reducing extended and point defect densities during this period, such defects still remain and with the push to lower off-cut angle substrates are in many cases seeing increases in prevalence. Thus, spectroscopic and imaging techniques for locating and identifying these defects are in high demand. Luminescence imaging and spectroscopy have both been utilized heavily in such work, yet simultaneously obtaining corresponding spectroscopic and spatial information from such defects is problematic. Here we report on hyperspectral imaging of electroluminescence from SiC pin diodes, whereby a stack of luminescence images are collected over a wide spectral range (400-900 nm), thereby providing the ability to both image distinct features and identify their corresponding spectral properties. This process is also equally applicable to collecting either photo- or electroluminescence from other materials or devices emitting in either the UV-Vis or NIR spectral range, as well as to reflectance, transmission or other imaging techniques.

Abstract: Electron-hole recombination-induced stacking faults have been shown to degrade the electrical characteristics of SiC power pin and MPS diodes and DMOSFETs with thick drift epitaxial layers. In this paper, we investigate the effects of bipolar injection induced stacking faults on the electrical characteristics of p+ ion-implanted high-voltage vertical-channel JFETs with 100-μm drift epilayers. The JFETs were stressed at a fixed gate-drain bipolar current density of 100 A/cm² for five hours, which led to degradation of the forward gate-drain p-n junction and on-state conduction. The degradation was fully reversed by annealing at 350 °C for 96 hours. Forward and reverse gate-source, transfer, reverse gate-drain, and blocking voltage JFET characteristics exhibit no degradation with bipolar stress. Non-degraded characteristics remain unaffected by annealing events. Consequently, should minority carrier injection occur in JFETs operating at elevated temperatures no stacking fault induced degradations are expected. This eliminates the need for specialty substrates with suppressed densities of basal plane dislocations in the fabrication of high-voltage SiC JFETs for high temperature applications.

Abstract: The effect of extended defects on carrier lifetime was investigated in 140 um thick 4H-SiC epilayers using whole wafer ultraviolet photoluminescence (UVPL) and microwave photoconductive decay (uPCD) mapping. Half-loop arrays (HLA) seen in the UVPL images showed a corresponding lifetime degradation in the same region, even before expansion of the HLAs to form SFs. Lifetime lowering was also seen for a defect comprising of a small 3C-SiC inclusion with a larger misoriented 4H-SiC region. Additionally, formation of slip planes after high temperature annealing was observed, which consequently shows a lifetime reduction in that region.

Abstract: Epitaxial graphene produced from SiC substrates exhibits a carrier mobility re- duction thought to arise from intercalated silicon. We present the results of density functional simulations and show that individual silicon atoms are highly mobile on and between graphene sheets, suggesting that thermally stable structures involving individual Si impurities are likely to result from the interaction of silicon with defects in the graphene sheets.

Abstract: Homo- and heteroepitaxial 3C-SiC layers were grown on 4H-SiC step-free mesas. The yields of smooth, defect-free mesas were ~ 17% for both intentionally and unintentionally doped films, while those with screw dislocations and multiple stepped surfaces were ~ 22%. The electronic and structural properties of the mesas were found on a micrometer-sized length scale using µ-PL and µ-Raman, respectively. 3C-SiC mesas were found to have complete 3C-SiC coverage with some of the mesas having electronic defects, while other mesas were found to be defect-free.

Abstract: In this paper, for the first time, we report a large area (1 cm2) SiC GTO with 9 kV blocking voltage fabricated on 100-mm 4H-SiC substrates with much reduced Basal Plane Dislocation (BPD) density. The static and dynamic characteristics are described. A forward drop of 3.7 V at 100 A (100 A/cm2) is measured at 25°C. A slight positive temperature coefficient of the forward drop is present at 300 A/cm2, indicating the possibility of paralleling multiple devices for higher current capability. The device exhibits extremely low leakage currents at high temperatures. The device has shown fast turn-on time of 53.9 nsec, and ~3.5 s of turn-off time, respectively. A stable forward voltage drop after electrical stress for >1000 hours has been achieved.

Abstract: Epitaxial graphene (EG) grown on the carbon-face of SiC has been shown to exhibit high carrier mobilities, in comparison to other growth techniques amenable to wafer-scale graphene fabrication. The transfer of large area (>mm2) graphene films to substrates amenable for specific applications is desirable. We demonstrate the dry transfer of EG from the C-face of 4H-SiC onto SiO2, GaN and Al2O3 substrates via two approaches using either 1) thermal release tape or 2) a spin-on, chemically-etchable dielectric. We will report on the impact that these transfer processes has upon the electrical properties of the transferred EG films.

Abstract: Since it was determined that the formation and expansion of intrinsic stacking faults (SFs) induced a drift in the forward voltage (Vf) in 4H-SiC bipolar devices, significant effort has been made to understand the driving force causing SF motion as well as the various associated luminescence processes. The observation that annealing of faulted SiC devices and epilayers induced SF contraction and a recovery of the Vf drift enabled the studying of the impact of various parameters such as temperature, injection level and operation time upon SF motion, the Vf drift and luminescence within the same device. However, these observations in many cases contradicted the previously reported driving force models. Here we report on a basic driving force model explaining SF expansion in hexagonal SiC as well as discuss the observation of green luminescence from C-core partial dislocations bounding the SFs that may indicate an enhanced mobility of point defects within forward biased SiC pin diodes.