Papers by Author: Jun Suda

Abstract: In this paper the impact of high temperature annealing on the formation of intrinsic defects in 4H-SiC such as Z_1/2 and EH_6/7 was examined. Therefore, three epitaxial layers with various initial concentrations of the Z_1/2- and EH_6/7-centers (10¹¹ – 10¹³ cm^-3) were investigated. It turns out that depending on the initial defect concentration the high temperature annealing leads to a monotone increase of the Z_1/2- and EH_6/7-concentration in a temperature range from 1600 to 1750°C. For a defined temperature above these values, the resulting defect concentration is independent of the sample’s initial values. Beside the growth conditions themselves such as C/Si ratio the thermal post-growth processing has a severe impact on the carrier lifetime which must be taken into account during device fabrication.

Abstract: It has been clarified that Z_1/2 center, a well known deep level as a lifetime killer, can be reduced to the concentration below 10¹¹ cm^-3 by thermal oxidation or C⁺ implantation plus Ar annealing. In this study, the authors investigate the trap-reduction phenomena systematically (experimentally), and propose a model to analyze the phenomena. Furthermore, prediction of the defect distributions is realized by solving a diffusion equation in accordance with the trap reduction model. This analytical model can explain almost all experimental data: oxidation-temperature dependence, oxidation-time dependence, and initial-Z_1/2-concentration dependence of the defect reduction. Based on these results, the authors accomplish to eliminate the Z_1/2 center to a depth of 100 μm in the sample with a relatively high initial-Z_1/2-concentration of 10¹³ cm^-3 by thermal oxidation at 1400°C for 16.5 h.

Abstract: The c- and a-lattice constants of nitrogen-doped 4H-SiC were measured in the wide temperature range (RT - 1100°C). The samples used in this study were heavily doped substrates and lightly-doped free-standing epilayers. The lattice constants at room temperature are almost identical for all the samples. However, the lattice contraction by heavy nitrogen doping was clearly observed at high temperatures, which indicates that the thermal expansion coefficients are dependent on the nitrogen concentration. The lattice mismatch (Δd/d) between a lightly-doped free-standing epilayer (N_d = 6x10¹⁴ cm^-3) and a heavily-doped substrate (N_d = 2x10¹⁹ cm^-3) was calculated as 1.7x10^-4 at 1100°C. The authors also investigated lattice constants of high-dose N⁺, P⁺, and Al⁺-implanted 4H-SiC. Reciprocal space mapping (RSM) was utilized to investigate the lattice mismatch and misorientation. The RSM images show the c-lattice expansion and c-axis tilt of the ion-implanted layers, irrespective of ion species. The authors conclude that the lattice expansion is not caused by heavy doping itself, but by secondary defects formed after the ion-implantation and activation-annealing process.

Abstract: Breakdown characteristics of 4H-SiC PiN diodes with various JTE structures have been investigated. By combining two-zone JTE and Space-Modulated JTE (SM-JTE), a breakdown voltage over 15 kV, corresponding to about 93 % of the parallel-plane breakdown voltage, was realized. The window of optimum JTE dose to obtain high breakdown voltage was widened, which indicates the robustness to the deviation of JTE dose. By comparing the breakdown voltage obtained by simulation and experimental results, impacts of the charge near the SiO₂/SiC interface are discussed.

Abstract: We demonstrate 4H-SiC bipolar junction transistors (BJTs) with an enhanced current gain over 250. High current gain was achieved by utilizing optimized device geometry as well as optimized surface passivation, continuous epitaxial growth of the emitter-base junction, combined with an intentional deep-level-reduction process based on thermal oxidation to improve the lifetime in p-SiC base. We achieved a maximum current gain (β) of 257 at room temperature and 127 at 250°C for 4H-SiC BJTs fabricated on the (0001)Si-face. The gain of 257 is twice as large as the previous record gain. We also demonstrate BJTs on the (000-1)C-face that showed the highest β of 439 among the SiC BJTs ever reported.

Abstract: We report the improvement of current gain in 4H-SiC bipolar junction transistors (BJTs) by using deposited oxides as a surface passivation layer. Various post-deposition annealing processes were investigated. We successfully demonstrated SiC BJTs with a high current gain (β) of 86 using deposited oxides annealed in NO. This is 70% higher current gain compared with that of BJTs with the same structure with conventional thermally-grown oxides.

Abstract: Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.

Abstract: Dislocations in 4H-SiC epilayers were imaged nondestructively by means of micro photoluminescence (-PL) mapping at room temperature. The one-to-one correspondence between the individual dislocations and the -PL mapping contrast has been consistently obtained. By analyzing the reduction of the intensity in the -PL mapping image performed at 390 nm (near band-edge emission), we were able to distinguish threading screw dislocations and threading edge dislocations. Furthermore, the contrast of dislocations in PL-intensity mapping image greatly depends on the carrier lifetimes of the 4H-SiC epilayers. Lifetimes longer than 0.5 s are essential to obtain a discernible contrast for the individual dislocations.

Abstract: In this study, new SiC-based heterojunction bipolar transistors (HBT) are proposed. An n-type AlN/GaN short-period superlattice (quasi-AlGaN) layer is grown on a SiC pn junction as a widegap emitter. By using quasi-AlGaN emitter, we have demonstrated successful control of band offset of AlGaN/SiC. Quasi-AlGaN/SiC HBT with an Al content over 0.5, which has no potential barrier to electron injection from an n-AlGaN emitter to a p-SiC base, exhibited a common-emitter current gain of β ~ 2.7, whereas the HBT with an Al content below 0.5 showed β ~ 0.1.

Abstract: In this paper, nitrided insulators such as N2O-grown oxides, deposited SiO2 annealed in N2O, and deposited SiNx/SiO2 annealed in N2O on thin-thermal oxides have been investigated for realization of high performance n- and p-type 4H-SiC MIS devices. The MIS capacitors were utilized to evaluate MIS interface characteristics and the insulator reliability. The channel mobility was determined by using the characteristics of planar MISFETs. Although the N2O-grown oxides are superior to the dry O2-grown oxides, the deposited SiO2 and the deposited SiNx/SiO2 exhibited lower interface state density (n-MIS: below 7x1011 cm-2eV-1 at EC-0.2 eV, p-MIS: below 6x1011 cm-2eV-1 at EV+0.2 eV) and higher channel mobility (n-MIS: over 25 cm2/Vs, p-MIS: over 10 cm2/Vs). In terms of reliability, the deposited SiO2 annealed in N2O exhibits a high charge-to-breakdown over 50 C/cm2 at room temperature and 15 C/cm2 at 200°C. The nitrided-gate insulators formed by deposition method have superior characteristics than the thermal oxides grown in N2O.