Papers by Author: Kuang Sheng

Abstract: Low channel mobility is one of the biggest challenges to commercializing SiC MOSFETs. Accurate mobility measurement is essential for understanding the mechanisms that lead to low mobility. The most widely used effective mobility measurements overestimate the inversion charge for devices that have high level of defects. Mobility measured by the Hall effect is more accurate; however the conventional Hall mobility measurement is tedious. In this work, we demonstrate a wafer-level Hall measurement technique, which is simple and convenient to implement. With this method, extensive study of the mobility degradation is possible.

Abstract: Reliability of the gate oxide on SiC is a pressing concern for deploying SiC MOS-based devices in real systems. While good projected oxide reliability was obtained recently under highly accelerated test conditions, indication that such projection may not be valid at lower operating fields was also reported. In this work, results from long-term TDDB stress (over 7 months) at 6 MV/cm and 300 °C on 4H-SiC MOS capacitors is reported. We confirm that lifetime projection from high-field data continues to be valid and no change in field acceleration factor is observed. The discrepancy between our results and the early prediction of poor reliability is examined.

Abstract: SiC MOSFET, as power device, can be expected to operate with high drain and high gate voltages, possibly leading to hot-carrier effect. However, hot-carrier degradation in a SiC MOSFET is difficult to detect because the as fabricated devices contain high level of defects. We report, for the first time, evidence of hot-carrier effect in 4H-SiC MOSFET. The result suggests that hot hole from impact ionization trapped in the oxide is the cause of the channel hot-carrier effect.

Abstract: A series of high voltage (HV) and low voltage (LV) lateral JFETs are successfully developed in 4H-SiC based on the vertical channel LJFET (VC-LJFET) device platform. Both room temperature and 300 oC characterizations are presented. The HV JFET shows a specific-on resistance of 12.8 mΩ·cm2 and is capable of conducting current larger than 3 A at room temperature. A threshold voltage drop of about 0.5 V for HV and LV JFETs is observed when temperature varies from room temperature to 300 oC. The measured increase of specific-on resistance with temperature due to a reduction of electron mobility agrees with the numerical prediction. The first demonstration of SiC power integrated circuits (PIC) is also reported, which shows 5 MHz switching at VDS of 200 V and on-state current of 0.4 A.

Abstract: This paper reports recent progress in the development of a vertical JFET, the purely vertical JFET based on trenched-and-implanted vertical JFET (TI-VJFET) approach that eliminates the need of epitaxial regrowth at middle of device fabrication and the need of a merged lateral JFET to control the vertical JFET. Different structures have been designed to target breakdown voltages ranging from 600V to 1.2kV. Vertical channel width uniformity has been studied, showing the feasibility of achieving below 0.1um variation for reasonably flat wafers of good thickness uniformity. Pitch size of the designs has been reduced compared to early report. Gate trench width has been reduced from 3.8um to 2.3um, aimed at increasing the device current capability. Fabricated device cells have been tested and packaged into multi-cell 30A TI-VJFETs which have been characterized of DC and switching characteristics at room and elevated temperatures. Very fast current rise/fall times of <10ns were observed from RT to 200°C. PSpice model for TI-VJFET has been developed and applied to the performance prediction of 3-phase SiC power inverter, suggesting a high efficiency 97.7% at 200°C junction temperature without using soft-switching scheme. Preliminary experimental demonstration of a PWM-controlled three-phase inverter based on SiC TI-VJFET power board is reported.

Abstract: This paper reports recent progress in the development of high power 4H-SiC BJTs based on an improved device design and fabrication scheme. Near theoretical limit high blocking voltage of VCEO=1,836 V has been achieved for 4H-SiC BJTs based on a drift layer of only 12 μm, doped to 6.7x1015 cm-3. The collector current measured for a single cell BJT with an active area of 0.61 mm2 is up to IC=9.87 A (JC=1618 A/cm2). The collector current is 7.64 A (JC=1252 A/cm2) at VCE=5.9 V in the saturation region, corresponding to an absolute specific on-resistance (RSP_ON) of 4.7 m9·cm2. From VCE=2.4 V to VCE= 5.8 V, the BJT has a differential RSP_ON of only 3.9 m9·cm2. The current gain is about 8.8 at Ic=5.3 A (869 A/cm2). This 4H-SiC BJT shows a V2/RSP_ON of 717 MW/cm2, which is the highest value reported to date for high-voltage and high-current 4H-SiC BJTs. A verylarge area 4H-SiC BJT with an active area of 11.3 mm2 is also demonstrated.