Papers by Author: Marc Meuris

Abstract: Interface quality plays a key role in solar cell applications. Interface recombination at the front and rear surfaces, which determine this quality, have significant effects on open circuit voltage and fill factor values. In this work, several surface treatments were applied on Cu(In,Ga)Se₂ (CIGS) surfaces to improve the interface quality. Besides, the passivation layer implementation was investigated to reduce interface recombination between the buffer and absorber layers.

Abstract: Copper indium gallium selenide/sulfide (CIGS) and copper zinc tin selenide/sulfide (CZTS) are two thin film photovoltaic materials with many similar properties. Therefore, three new processing steps – which are well-known to be beneficial for CIGS solar cell processing – are developed, optimized and implemented in CZTS solar cells. For all these novel processing steps an increase in minority carrier lifetime and cell conversion efficiency is measured, as compared to standard CZTS processing. The scientific explanation of these effects is very similar to its CIGS equivalent: the incorporation of alkali metals, ammonium sulfide surface cleaning, and Al₂O₃ surface passivation leads to electrical enhancement of the CZTS bulk, front surface and reduced front interface recombination, respectively.

Abstract: The last decennia, a lot of effort has been made to introduce new channel materials in a Si process flow. High mobility materials such as Ge need a good gate stack passivation in order to ensure optimal MOSFET operation. Several routes for passivating the Ge gate stack have been explored in the last years. We present here the S-passivation of the Ge gate stack: (NH₄)₂S is used to create a S-terminated Ge surface. In this paper the S-treatment is discussed. The S-terminated Ge surface is not chemically passive but can still react with air. After gate oxide deposition, the Ge-S bonds are preserved and an adequate passivation is found for pMOS operation.

Abstract: The Si transistor has dominated the semiconductor industry for decades. However, to fulfill the demands of Moore’s law, the Si transistor has been pushed to its physical limits. Introducing new materials with higher intrinsic carrier mobility is one way to solve this problem. Ge, GaAs and InGaAs are known for their high mobilities and are therefore suitable candidates for replacing Si as a channel material. However, introduction of new materials raises new issues. For Si processing, several steps such as cleaning, etching and stripping are based on wet treatments. The knowledge of etch rates of the semiconductor material is of great importance. In this paper, etch rates of Ge, GaAs and InGaAs in several chemical solutions are studied. A comparison of the etch rates is made between the materials.

Abstract: The formation of shallow junctions in germanium substrates, compatible with deep submicron CMOS processing is discussed with respect to dopant diffusion and activation and damage removal. Examples will be discussed for B and Ga and for P and As, as typical p- and n-type dopants, respectively. While 1 to 60 s Rapid Thermal Annealing at temperatures in the range 400-650oC have been utilized, in most cases, no residual extended defects have been observed by RBS and TEM. It is shown that 100% activation of B can be achieved in combination with a Ge pre-amorphisation implant. Full activation of a P-implant can also be obtained for low-dose implantations, corresponding with immobile profiles. On the other hand, for a dose above the threshold for amorphisation, a concentration-enhanced diffusion of P occurs, while a lower percentage of activation is observed. At the same time, dose loss by P out-diffusion occurs, which can be limited by employing a SiO2 cap layer.