Papers by Author: Masayuki Wada

Abstract: Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.

Abstract: In this work the dynamics of particle removal by aerosol spray is investigated. Local dwell time of spray cleaning is calculated numerically from the process conditions, and some striking topological similarities between the particle removal efficiency and dwell time profiles are observed. The particle removal rates, defined as the normalized speed of particle removal, are not constant during a typical process, with the highest removal rate for the first tens of milliseconds and a temporal decay as time elapses. Increasing N₂ flow rate results in an enhancement in both the particle removal efficiency and the particle removal rate.

Abstract: With the continuous decrease of feature size of semiconductor devices new process related challenges must be overcome continuously. One of the key issues for technology development is to have the proper metrology in place to evaluate the myriad process steps fast and accurately. Sometimes the mere existence of a particular metrology is not enough because of cost and throughput issues. The goal of this paper is to show that simply by monitoring the background signal of a light scattering tool, certain process optimizations and monitoring can be done much faster while bringing down the cost significantly. We focus particularly on post I/I strip optimization in this paper.

Abstract: In the very near future 32(28)-nm node device technology innovations will enter high volume manufacturing. New materials and structures, e.g. high-k (HK), high-k cap (HK cap), metal gate (MG) and SiGe channel, are being highly considered. Requirements for wet processing are varied according to metal-first or metal-last integration schemes. [1, 2, 3] One of the biggest challenges in wet processing for implementing new materials and structures is to achieve both high selectivity and low substrate loss. At some wet cleaning or etching processes, standard chemicals, e.g. APM, HF and O3, can be accommodated by optimizing the chemical condition. However, photoresist (PR) strip processes require the development of new chemicals or techniques, since SPM does not have sufficient compatibility against presently reported materials. This study focused on the PR strip technique via the dissolution and swelling effects in solvent, and an applicable process technique and its effectiveness for 32(28)-nm and beyond device fabrication is reported.

Abstract: The introduction of metal gates and high-k dielectrics in FEOL and porous ULK dielectrics in BEOL presents severe issues [1] and leads to the requirement of new chemistries and processes. A major challenge in cleaning is the removal of photoresist (PR) in both FEOL and BEOL. In current semiconductor device fabrication flow, the photoresist strip process in FEOL is mostly achieved by applying a sequence of plasma ashing followed by a wet-clean step with sulfuric-peroxide mixture (SPM). But in general, ashing leads to strong oxidation or etching of silicon substrate. Hence, several approaches for ashless PR strip have been reported, such as hot SPM [2] and the combination of a pre-treatment using high velocity CO2 aerosol [3].

Abstract: High-k gate dielectrics (HK), such as HfO2 or HfSiON, are being considered as the gate dielectric option for the 45nm node and beyond. In order to alleviate the Fermi-level pinning issue and to enhance the CET (Capacitive Effective Thickness) by generating the depletion layer in poly-Silicon gate, metal gate electrodes with proper work functions (WF) have to be used on the high-k dielectrics.

Abstract: Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

Abstract: Strained silicon engineering was first used at the 90-nm node. Nowadays, a series of techniques has seen wide-spread use and many derivatives are available because of their ease of integration and cost-effective features [ , ]. As a main part of stressor technique, embedded SiGe-S/D technology is reported to improve the pMOSFET drive current [ , ].

Abstract: Nanostructures with high aspect ratios, HAR, (ratio of height to lateral feature size) are of interest for many applications. One of the immediate advantages is the large surface area of these structures. In the field of DRAM manufacturing for example, the capacitance of cylindrical DRAM capacitors increases linearly with height. Wet etching and drying of these fragile high aspect ratio structures without lateral collapse (stiction) is a big challenge for the fabrication of DRAM capacitors. The problem with HAR structures is stiction during drying [1]. In order to reduce stiction by improvement of drying techniques, a good metric to quantify the occurrence of stiction is needed. However, currently used methods like SEM or brightfield defect inspection are extremely time-consuming.

Abstract: High velocity aerosol cleaning using ultrapure water or dilute aqueous solutions (e.g. dilute ammonia) is common in semiconductor IC fabrication [1]. This process combines droplet impact forces with continuous liquid flow for improved cleaning efficiency of sub-100nm particles. As with any physically enhanced cleaning process, improved particle removal can be accompanied by increased substrate damage, especially to smaller (<80nm) features [2]. Solvents such as N-methylpyrrolidone (NMP) and tetrahydrofurfuryl alcohol (THFA) are used for resist strip applications [3]. It is possible, and sometimes useful, to deliver these solvents through the same spray nozzle normally used for aqueous spray cleaning. In this presentation we explore the particle removal and substrate damage performance of 2-ethoxyethanol (EGEE), NMP and THFA as used in a conventional aerosol spray cleaning system