Papers by Author: Narcis Mestres

Abstract: Graphene is a 2D material with potential for almost any purpose, thanks to a combination of excellent characteristics, e.g. high electrical conductivity. Graphene grown on SiC wafers is one of the promising routes for graphene integration into planar technology electronic applications. Synthesis is based on the decomposition of a SiC single crystal surface at high temperature, where Si-terminated SiC substrates require the formation of the C buffer layer. In spite of numerous experimental and theoretical works the understanding and control upon crucial factors such as step and terrace stability or surface roughening is far from been fully comprehended and then technologically optimized. We present experimental results on the deposition of graphene onto Si-terminated 6H-SiC. We analyze the effect of ex situ and in situ conditionings of the SiC surface in the thermal decomposition and reconstruction of the SiC terraces, toward higher control upon the growth process of graphene films.

Abstract: SiC crystal is a wide band gap material of high hardness and chemical inertness. Graphene is nowadays a ubiquitous 2D material that would revolutionize many applications. Combining the characteristics of SiC and graphene higher performance and efficiency are expected, e.g. for high frequency electronic devices. The obtaining of graphene directly on SiC substrates by a single step thermal decomposition process is promising, but optimal standardized conditions are not established. We present the use of chemical-mechanical polishing (CMP) as a pre-graphene growth SiC conditioning to enable deep comprehension of the mechanisms of SiC decomposition and control towards selective formation of graphene.

Abstract: In this paper, the integration of HfO2 onto SiC has been investigated via a number of different test structures. Capacitors consisting of HfO2 on Si, SiC, Si/SiC and SiO2/SiC have been fabricated and electrically tested. The new HfO2/Si/SiC capacitors provide the greatest breakdown electric field of 3.5 MV/cm, whilst leakage currents are minimised through the insertion of the narrow bandgap material. The Si layer, which is wafer bonded to the SiC, is proven to be stress free through Raman spectroscopy, whilst TEM and EDX prove that the interface is free of contaminants.

Abstract: Epitaxial graphene growth is significantly different depending on the polarity of the 6H-SiC surface: Si- or C-face. On the Si-face, a uniform coverage of few layers on the whole sample can be obtained, but with electrical properties disturbed by the presence of a Carbon-rich buffer layer at the interface. On the contrary, on the C-face, we demonstrated that almost free-standing very large monolayers of graphene can be obtained by covering the sample with a graphitic cap during the growth.

Abstract: In this study, a SiC on insulator growth is optimized, in order to electrically isolate the active structural layer towards the substrate. High quality single crystalline SiC was grown on SOI and SIS substrates. Smooth surface, low stress and bowing, confirmed by microscopy techniques, SEM, AFM, X-Ray diffraction and Raman spectroscopy, have been obtained. SiC electrostatic resonators on insulated substrates were also fabricated, and electrically driven. These results demonstrate that this material is very promising for MEMS application requiring isolation from the substrate and operation in harsh ambient.

Abstract: We report a comparative investigation of few layers graphene grown on 6H, 4H and 3C-SiC substrates. We show that the size of the graphitic domains depends more on the <0001> SiC surface orientation than the polytypism.

Abstract: Silicon Carbide has proven its relevance for various MEMS and sensors devices applications. This paper presents the fabrication and the first test results of 3C-SiC electrostatic resonators actuated by applying a combination of AC and DC voltages. The recipe used for the fabrication has taken the advantage of the starting material, 3C-SiC grown on Si, which allows us to use the Si substrate as sacrificial layer to release the structures. Resonators have been fabricated by a two-step process, combining RIE ICP etching with HF wet etching. Resonators have been successfully electrostatically actuated in air-ambient condition. The resonance frequencies were clearly identified, although capacitive current created by actuation was not detected.

Abstract: In prior work we have proposed a mobility model for describing the mobility degradation observed in SiC MOSFET devices, suitable for being implemented into a commercial simulator, including Coulomb scattering effects at interface traps. In this paper, the effect of temperature and doping on the channel mobility has been modelled. The computation results suggest that the Coulomb scattering at charged interface traps is the dominant degradation mechanism. Simulations also show that a temperature increase implies an improvement in field-effect mobility since the inversion channel concentration increases and the trapped charge is reduced due to bandgap narrowing. In contrast, increasing the substrate impurity concentration further degrades the fieldeffect mobility since the inversion charge concentration decreases for a given gate bias. We have good agreement between the computational results and experimental mobility measurements.

Abstract: We have performed nitrogen and phosphorus co-implants at room temperature to obtain high n-type carrier concentration layers in SiC. An inductive heating RTA furnace has been used for the activation annealing. The influence of the temperature ramp parameters such as rise/decrease temperature speed and intermediate annealing steps on the dopant activation rate and surface morphology have been investigated. A reduction of the temperature ramp slope reduces the surface roughness by 50%. Inclusion of a pre-activation annealing step at low temperatures (1300°C) further reduces the surface roughness. However, the use of slower ramps or an intermediate annealing step during ramp up reduces the free carrier concentration. The faster the ramp up, the higher the activation rate and the resulting doping. We also demonstrate that the inclusion of a postactivation annealing at intermediate temperatures (1150°C) reduces significantly the surface roughness. In addition, the use of this post-annealing treatment does not degrade the activation rate nor the carrier Hall mobility, and activation rates close to 100% have been obtained.