Papers by Author: Nicolas G. Wright

Abstract: In this study we report interface and carrier transport behaviour in Al/HfO2/SiO2/SiC MIS structure. The density of the interface states (Dit) and the oxide trapped charges (Not) are found to be ~7 x 1011 eV-1cm-2 @ Ec-Et = 0.2 eV, and ~ 4.8 x 1011 cm-2. The temperature dependencies on gate current density are explored to study the different charge transport mechanisms through the HfO2-based dielectric stack on 4H-SiC. In the low voltage region, the conduction mechanism is controlled by a space charge limited or electronic hopping conduction process. Beyond this region (1.25 MV/cm 2.5 MV/cm), and at higher temperatures Schottky emission (SE) fits the data very well. The barrier height is found to be ~1.5 eV, which is higher than the value for just HfO2 on SiC

Abstract: Silicon Carbide (SiC) power devices are increasingly in demand for operations which require ambient temperature over 300°C. This paper presents circuit applications of normally-on SiC VFETs at temperatures exceeding 300°C. A DC-DC boost converter using a 4H-SiC VJFET and a SiC Schottky Diode was fabricated and operated up to 327°C. A power amplifier achieved a voltage gain of 3.88 at 27°C dropping to 3.16 at 327°C. This 20 % reduction is consistent with the fall in transconductance of the device.

Abstract: Zener diodes are widely used in electrical barriers to protect equipment operating in a potentially explosive atmosphere. Although normally not conducting, the zeners must have a high power rating so that their junction temperature meets safety factors when shunting the maximum fuse current. This often requires two or three lower voltage commercial zeners connected in series. Silicon carbide diodes have much higher thermal conductivity and maximum allowed junction temperature, so it should be possible to use one SiC zener in the place of two or three commercial diodes and/or allow use of higher fuse ratings. Low voltage SiC Zener diodes were fabricated and tested to evaluate potential benefits of their application as a component of intrinsically safe barriers. The diodes demonstrated mixed avalanche-tunnel breakdown at reverse bias voltages of 23 V with positive temperature coefficients of breakdown voltages of about 0.4 mV/°C. The diodes with mesa area of 4×10-4cm2 had maximum DC Zener current of 1.2 A and were capable of operating at ambient temperatures up to 500°C.

Abstract: High voltage 4H-SiC Schottky diodes with single-zone junction termination extension (JTE) have been fabricated and characterised. Commercial 4H-SiC epitaxial wafers with 10, 20 and 45 +m thick n layers (with donor concentrations of 3×1015, 8×1014 and 8×1014 cm-3, respectively) were used. Boron implants annealed under argon flow at 1500°C for 30 minutes, without any additional protection of the SiC surface, were used to form JTE’s. After annealing, the total charge in the JTE was tuned by reactive ion etching. Diodes with molybdenum Schottky contacts exhibited maximum reverse voltages of 1.45, 3.3 and 6.7 kV, representing more than 80% of the ideal avalanche breakdown voltages and corresponding to a maximum parallel-plane electric field of 1.8 MV/cm. Diodes with a contact size of 1×1 mm were formed on 10 +m thick layers (production grade) using the same device processing. Characterisation of the diodes across a quarter of a 2-inch wafer gave an average value of 1.21 eV for barrier heights and 1.18 for ideality factors. The diodes exhibited blocking voltages (defined as the maximum voltage at which reverse current does not exceed 0.1 mA) higher than 1 kV with a yield of 21 %.

Abstract: The formation of two-dimensional electron gases (2DEG) at the polytypic 6H/3C heterojunction is investigated. The main of study was to obtain the properties of the 3C/6H structure using Technology Computer Aided Design (TCAD) software. The electron-density distribution and conduction band profile in 6H/3C SiC heterojunction are calculated as a function of temperature. Simulation of these hetero-junctions has concentrated on the I-V behaviour over a range of temperatures between 350 and 650 K. We show that the device characteristics are substantially degraded at high temperatures and this will limit the use of these devices to moderate temperature applications.

Abstract: This report investigates the advantages of high-k materials as gate dielectrics for high power SiC trench MOSFET devices, by means of TCAD simulation. The study makes a comparison between the breakdown characteristics of gate dielectrics comprising SiO2, HfO2 and TiO2. I-V and Transfer functions show forward characteristics with on-state resistivity of 8.27 m*⋅cm2, 8.65 m*⋅cm2, 15.8 m*⋅cm2 for the respective devices, at a gate voltage of 20 V. The threshold voltage is 10 V for all devices. The blocking voltage for the HfO2 and TiO2 is increased from 1800 V (for the SiO2 device) to 2200 V. With a peak electric field of 12 MV/cm through the oxide of the SiO2 device is reduced to 3.2 MV/cm for the HfO2 and 2.3 MV/cm for the TiO2 devices.

Abstract: 4H-SiC depletion mode (normally-on) VJFETs were fabricated and characterised at temperatures up to 377 °C. The device current density at drain voltage of 50 V drops down from 54 A/cm2 at room temperature to around 42 A/cm2 at 377 °C which is a 20 % reduction in drain current density. This drop in drain currents is much lower than previously reported values of a 30 % drop in JFETs at high temperatures. The average temperature coefficient of the threshold voltage was found to be -1.36 mV/°C which is smaller than for most Si FETs. We have found that these devices have shown good I-V characteristics upto 377 °C along with being able to retain its characteristics on being retested at room temperature.

Abstract: In this paper a novel approach to the design and fabrication of a high temperature inverter module for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over 200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, doublesided cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.

Abstract: The characteristic of trap assisted conduction and interface states for a Pd/TiO2/SiO2/SiC structure has been investigated at temperatures up to 500 °C. Thermally oxidized Ti/SiO2 gate capacitors fabricated by dry oxidation in O2 were studied. The electrical measurements show the current conduction through this capacitor structure is controlled by a trap assisted conduction mechanism at low bias and the barrier height (φA) between the metal and the TiO2 was extracted. The current density in the dielectric stacks is also shown to be strongly temperature dependent. The results demonstrate that the formation of a charge dipole under the Pd contact is responsible for barrier height and not any changes in the behaviour of the TiO2 film itself, such as a change in concentration of trapping centres. The reported results indicate electron trapping property across the SiO2 layer is consistent with fitting experimental results to the trap assisted conduction model.

Abstract: We present the variation of trap assisted conduction current through a dielectric stack comprising TiO2 and SiO2 on SiC as a function of both temperature and hydrogen gas concentration. We show that the current can be modeled by the use of a single barrier height across the temperature range of interest (>300oC ambient). Upon exposure to hydrogen gas, this barrier height is reduced from 0.405 to 0.325eV, whilst the density of traps in the bulk of the TiO2 remains unaffected. We conclude that the formation of a charge dipole layer under the palladium contact is responsible for this change in barrier height, as has been observed in Schottky diode sensor structures. Further, sensing the gas concentration by monitoring of the trap assisted conduction current appears not to be influenced by the existence of interfacial traps, offering the chance to fabricate low drift sensors for deployment in extreme environments.