Papers by Author: Shailaja P. Rao

Abstract: Homoepitaxial growth of 4H-SiC on on-axis Si-face substrates is reported using hydrogen chloride together with silane and ethylene. In this study, the main process parameters, such as temperature, Cl/Si ratio, C/Si ratio, Si/H2 ratio and ramp up conditions, were studied in detail to understand their effects on the growth mechanisms. Two different optimal epitaxial growth conditions were found. Silicon rich conditions and a high Cl/Si ratio were the key parameters to grow thick homoepitaxial layers with a very low background doping concentration and a growth rate higher than 20 μm/h.

Abstract: Crystal growth of 6H-SiC in two non-basal directions is reported. The two explored surfaces are the {1-103} plane, named qC-face, and the {1-10-3} plane, named qSi-face. The asgrown bulk surfaces exhibit a smooth structure with a small ridging effect originating from the miscut of the seed crystals. Layers, epitaxially grown on the chemically-mechanically polished qCface, nicely replicate the original crystal structure and show no sign of polytype mixing. Lowtemperature photoluminescence measurements collected on the epilayers exhibit near bandedge spectral characteristics indicative of good quality 6H-SiC.

Abstract: Post-implant annealing of Al implanted 4H-SiC has been performed in the temperature range from 1600°C to 1750°C. Annealing was conducted in a hot-wall CVD reactor using a silanerich ambient. Ar was used as the carrier gas to deliver the silane to the annealing zone where the sample was heated via RF induction. The resulting annealed surfaces exhibited a step-bunch free, smooth morphology when viewed on SEM and AFM. The maximum surface roughness as measured via AFM was 0.65 nm RMS for the sample annealed at 1750°C.

Abstract: This work reports the realization and characterization of 4H-SiC p+/n diodes with the p+ anodes made by Al+ ion implantation at 400°C and post-implantation annealing in silane ambient in a cold-wall low-pressure CVD reactor. The Al depth profile was almost box shaped with a height of 6×1019 cm-3 and a depth of 160 nm. Implant anneals were performed in the temperature range from 1600°C to 1700°C. As the annealing temperature was increased, the silane flow rate was also increased. This annealing process yields a smooth surface with a roughness of the implanted area of 1.7 - 5.3 nm with increasing annealing temperature. The resistivity of the implanted layer, measured at room temperature, decreased for increasing annealing temperatures with a minimum value of 1.4 0-cm measured for the sample annealed at 1700°C. Considering only the current-voltage characteristic of a diode that could be modeled as an abrupt p/n junction within the frame of the Shockley theory, the diode process yield and the diode leakage current decreased, respectively, from 93% to 47% and from 2×10-7 Acm-2 to 1×10-8 Acm-2 at 100 V reverse bias, for increasing post implantation annealing temperature.

Abstract: Commercial on-axis wafers of 4H-SiC(0001) were etched in a standard reactor for chemical vapor deposition (CVD) using molecular hydrogen flux in order to improve the structure and morphology of the surface. The substrate temperature during etching was varied from 1400 to 1600°C. Characterization of the surface morphology was performed using optical and atomic force microscopy (AFM). Low-energy electron diffraction (LEED) and X-ray photoelectron spectroscopy (XPS) were also used to examine the surface structure and chemical composition of the samples. The sample of best quality was obtained for an etching temperature of 1400°C. Its surface is ° × 30 ) 3 3 ( R reconstructed and covered by an ordered “silicate” layer. Increasing the substrate temperature during etching to 1500°C leads to enhanced step-bunching and the formation of macroterraces. At 1600°C distinct depressions appear on the surface, presumably from etching of structural defects such as screw dislocations. Subsequent annealing at 1000°C in ultra-high vacuum (UHV) removes the surface oxide and produces the ° × 30 ) 3 3 ( R surface phase of clean 4HSiC( 0001).

Abstract: Al+ implanted p+/n 4H-SiC diodes were realized via planar technology. The p+/n junctions were obtained by hot implantation at 400°C, followed by a post implantation annealing at 1600°C in Silane ambient. 136 diodes and other test structures were measured: the current voltage^curves and the resistivity of the implanted layer were investigated at room temperature. The majority of the measured diodes had a turn on voltage of about 1.75 V, a forward characteristic with exponential trend and ideality factor equal to 1.2, and a very low spread in the distribution of the reverse leakage current values at –100V. The average reverse leakage current value is (9.7 ± 0.4) × 10-9 A/cm2. The breakdown voltage of these diodes approached the theoretical value for the use epitaxial 4H-SiC layer, i.e. 0.75 – 1.0 kV. All these positive results are penalized by the high resistivity value of the implanted Al+ layer, which amounts to 11 W·cm that is one order of magnitude higher than the desired value.

Abstract: Hydrogen chloride (HCl) was added to a standard SiC epitaxial growth process as an additive gas. A low-pressure, hot-wall CVD reactor, using silane and propane precursors and a hydrogen carrier gas, was used for these experiments. It is proposed that the addition of HCl suppresses Si cluster formation in the gas phase, and possibly also preferentially etches material of low crystalline quality. The exact mechanism of the growth using an HCl additive is still under investigation, however, higher growth rates could be obtained and the surfaces were improved when HCl was added to the flow. The film morphology was studied using SEM and AFM and the quality with LTPL analysis, which are reported.