Papers by Keyword: Breakdown Voltage

Abstract: A classical implementation of the field plate technique is the oxide ramp termination. This paper presents for the first time a comparison between SiC and diamond Schottky barrier diodes (SBD) using this termination. The influences of the ramp angle and oxide thickness on the diodes electrical performance are investigated for both punch-through (PT) and non punch-through (nPT) structures. The efficiency of the termination is also evaluated.

Abstract: This paper demonstrates the breakdown voltage characteristics of different edge termination structures including aluminum (Al)-deposited guard ring and Al-deposited guard ringassisted field limiting ring (FLR) for a 4H silicon carbide (SiC) Schottky barrier diode (SBD). In order to investigate the application feasibility of the Al-deposited junction termination to a high breakdown voltage SiC-SBD, two types of SiC-SBDs are fabricated using conventional photolithography, electron beam evaporation, and thermal treatment techniques without ion implantation and thermal oxidation procedures. The breakdown voltage characteristics of the SiCSBDs are significantly dependent on the Al-deposited edge termination. The SiC-SBD without the Al-deposited edge termination shows less than 250 V breakdown voltage, while the Al-deposited guard ring and Al-deposited guard ring-assisted FLR structures show roughly 700 V and 1200 V breakdown voltages, respectively. The prominent improvement in the breakdown voltage characteristics is attributed to the electric field lowering at the Schottky contact edge by the Al deposition edge termination.

Abstract: 4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.

Abstract: The nano-characterization of thermal oxides grown on 4H-SiC is for the first time presented and analysed to derive its reliability. The dielectric breakdown (BD) kinetics of silicon dioxide (SiO2) thin films thermally grown on 4H-SiC has been determined by comparison between I-V measurements on large-area (up to 1.96×10-5 cm2) metal-oxide-semiconductor (MOS) structures and conductive atomic force microscopy (C-AFM) with a resolution of a few nanometers. C-AFM clearly images the weak breakdown single spots under constant voltage stresses. The stress time on the single C-AFM tip dot has been varied from 1×10-3 to 1×10-1 s. The density of BD spots, upon increasing the stress time, exhibits an exponential trend. The Weibull slope and the characteristic time of the dielectric BD events were so determined by direct measurements at nanometer scale demonstrating that the percolation model is valid for thin thermal oxide layers on 4H-SiC (5-7nm), but it fails for larger thicknesses (10 nm).

Abstract: Ti/4H-SiC Schottky barrier diodes were fabricated under 500, 750, 1000 °C thermal treatment conditions. After the heat treatment at 750 °C, formation of TiC(111) and Ti5Si3(210) phases was confirmed by XRD analysis. Formation of Ti carbide and silicide phase increased breakdown voltage VB from 545 V to 830 V. An improvement of breakdown voltage (VB) was observed in case of the thermal treatment in nitrogen ambient at 750 °C for 2 min. Ideality factor (n), specific on resistance (Ron), and Schottky barrier height (Φb) were 1.04, 2.7 m-cm2, 1.33 eV respectively.

Abstract: ZnO-Pr6O11-Dy2O3-based varistor ceramics doped with 0~1.5 mol% La2O3 were fabricated by a conventional ceramic method. All the samples were sintered at 1350 oC
for 2 h. The phase composition and microstructure of the ceramic samples have been investigated by XRD, SEM and EDS. The results of SEM micrographs indicated that the La2O3 additives can promote ZnO grain’s growth, and the rare earth elements dispersed mainly in the intergranular phase observed by EDS. The electrical properties of the samples determined by the V-I curves revealed that the breakdown voltage of samples decreases from 508 V/mm to about 100 V/mm with the increase of La2O3, and the nonlinear exponent also decreases from 20.2 to 13.2. The typical leakage current is about 10.2 μA for the sample doped with 0.5 mol% La2O3.

Abstract: A series of CuW60Cr15 composites with different Cr particle size ranging from 43μm to147μm in diameter have been prepared by infiltration. The results show that the size of Cr particles plays an important role on the microstructures and the properties of the CuW60Cr15 composite. Fine Cr particle changes not only the size of the isolated CrCu alloy zone but also the structure of the skeletons of the composite obviously. Fine Cr particles increase not only the maximum and the minimum but also the mean value of breakdown voltage. Although the maximum value of chopping currents remains almost constant while Cr particles become finer, the minimum and the mean values of chopping current discernible decrease in the CuW60Cr15 composites. It can be seen from the SEM photos of the composites after arcing that the size and its location of the arc spot determines the chopping current value of the composites.

Abstract: GaN PiN diodes with a 4 μm Si-doped n--GaN drift layer (n~7×1016 cm-3) were grown on free-standing GaN using metalorganic chemical vapor deposition. Atomic force microscopy showed smooth surfaces with a step structure indicating good 2D growth. The dislocation density and impurity incorporation in the drift layer were remarkably reduced compared to a similar diode structure grown on sapphire. The full width at half maximum of the (0002) rocking curve was 79 arcsec, much smaller than 230 arcsec for the heteroepitaxial structure. The diodes on GaN demonstrated rectification up to –265 V, corresponding to a critical electric field ~2.7×106 V/cm. The maximum value of the figure of merit is ~2.4 MW cm-2, which represents a 2.2× improvement over the diodes on sapphire.

Abstract: 4H-SiC epilayer channel MOSFETs are fabricated. The MOSFETs have an n- epilayer channel which improves the surface where the MOS channel is formed. By the optimization of the epilayer channel and the MOSFET cell structure, an ON-resistance of 12.9 m
cm2 is obtained at VG = 12 V (Eox = 2.9 MV/cm). A normally-OFF operation and stable avalanche breakdown is obtained at the drain voltage larger than 1.2 kV. Both the ON-resistance and the breakdown voltage increase slightly with an increase in temperature. This behavior is favorable for high power operation. By the evaluation of the control MOSFETs with n+ implanted channel, the resistivity of the MOS channel is estimated. The MOS channel resistivity is proportional to the channel length and it corresponds to an effective channel mobility of about 20 cm2/Vs.

Abstract: Silicon carbide static induction transistors with submicron buried p+ gate (SiC-BGSITs) have been successfully developed through innovative fabrication process. A submicron buried p+ gate structure was fabricated by the combination of submicron trench dry etching and epitaxial growth process on a trench structure. As the device performance is mainly determined by the width of the p+ gate region and the spacing between two adjacent p+ gate regions, corresponding to the width of n- channel, we have optimized these parameters carefully using a device simulator. The breakdown voltage VBR and specific on-resistance RonS of the fabricated BGSIT were 700 V at a gate voltage VG = –12 V and 1.01 m/·cm2 at VG = 2.5 V and a drain current density JD = 200 A/cm2, respectively. This RonS is the lowest on-resistance for ~ 600V class power switching devices, including other wide-bandgap materials such as GaN.