Papers by Keyword: CMP

Abstract: Chemical mechanical polishing (CMP) is a widely adopted technique to achieve high level of global and local planarity required in modern integrate circuit (IC) industries, wherein the pad properties weigh heavily on the final performance. A preliminary two-dimensional wafer-scale flow model for CMP is presented considering the roughness, the elasticity, as well as the porosity of the pad. Numerical simulations were conducted to show the slurry flow features’ variations due to pad parameters change. The results show that the porosity of the pad is conducive to slurry delivering, and small porous parameter will lead to prominent increase of load capability, accounting for larger material removal rate (MRR) whilst the elasticity of the pad has a more complex influence. The rough surface carries additional fluid in the valleys of the polishing pad thereby provide some chemical reactions. The model will shed lights on the mechanism of CMP process, which is for a long time considered as a difficult circle to square.

Abstract: Subsurface residual stresses of tungsten films induced by Chemical Mechanical Polishing (CMP) processes were investigated by the Grazing Incident X-Ray Diffraction (GIXRD). Basis of the GIXRD measurement was introduced and the experiments were conducted for residual stress of tungsten film measurements. Experimental procedures of the GIXRD measurements were presented. The obtained residual stresses value of tungsten films from 800 nm to 400 nm varies from 1086.1 ± 105.2 MPa to 1670.6±103.4 MPa prior and after CMP process.

Abstract: Silicon carbide (SiC) is a wide band gap semiconductor being developed for high temperature, high power, and high frequency device applications. For the manufacturing of SiC to semiconductor substrate, many researchers have studied on the subject of SiC polishing. However, SiC faces many challenges for wafer preparation prior to epitaxial growth due to its high hardness and remarkable chemical inertness. A smooth and defect free substrate surface is important for obtaining good epitaxial layers. Therefore, hybrid process, chemical mechanical polishing (CMP) has been proposed to achieve epi-ready surface. In this paper, the material removal rate (MRR) is investigated to recognize how long the CMP process continues to remove a damaged layer by mechanical polishing using 100 nm sized diamond, and the authors tried to find the dependency of mechanical factors such as pressure, velocity and abrasive concentration using single abrasive slurry (SAS). Especially, the authors tried to get an epi-ready surface with mixed abrasive slurry (MAS). The addition of the 25nm sized diamond in MAS provided strong synergy between mechanical and chemical effects resulting in low subsurface damage. Through experiments with SAS and MAS, it was found that chemical effect (KOH based) was essential and atomic-bit mechanical removal was efficient to remove residual scratches in MAS. This paper concluded that SiC CMP mechanism was quite different from that of relatively soft material to achieve both of high quality surface and MRR.

Abstract: Lithium niobate (LN, LiNbO3) is a kind of artificial crystal with piezoelectricity, pyroelectricity and ferroelectricity, which has been widely used in electron components. The large difference in thermal expansion coefficients between Si and LN causes a serious thermal stress during the thermal-pressure bonding process. Therefore room temperature bonding would be the best candidate to make strong and stress-free interface between Si and LN. However, room temperature bonding requires lower surface roughness (Ra<2nm) and lower defects on the LN wafer surface than those of thermal bonding. Chemical mechanical polishing (CMP) process helps LN to obtain the high quality surface and thin wafer suited in room temperature bonding. The LN wafer was polished using colloidal silica slurry, resulting in high material removal rate (MRR) and fine surface quality under the condition of low pH, high abrasive concentration and low flow rate. The polishing mechanism of LN was discussed by mechanical, chemical and thermal analysis.

Abstract: Chemical mechanical polishing (CMP) has been used as planarization process in the fabrication of semiconductor devices. The CMP process is required to planarize the overburden film in an interconnect process by high relative velocity between head and platen, high pressure of head and chemical effects of an aqueous slurry. But, a variety of defects such as dishing, delamination and metal layer peering are caused by CMP factors such as high pressure, pad bending and strong chemical effect. The electrical energy of the electro-chemical mechanical planarization (ECMP) dissolves copper (Cu) solid into copper ions electrochemically in an aqueous electrolyte. The dissolved copper complex layer or passivation layer is removed by the mechanical abrasions of polishing pad and abrasive. Therefore the ECMP process realizes low pressure processing of soft metals to reduce defects comparing to traditional CMP process. But, if projected metal patterns were removed and not remained on whole wafer surface in final processing stage, Cu layer could not be removed by ECMP process. The two-step process consists of the ECMP and the conventional CMP used in micro patterned Cu wafers. First, the ECMP process removed several tens 'm of bulk copper on Cu patterned wafer within shorter process time than the Cu CMP. Next, residual Cu layer was completely removed by the Cu CMP under low pressure. Total time and process defects are extremely reduced by the two-step process.

Abstract: We report SiC wafer polishing study to achieve high throughput with extremely flat, smooth and damageless surface. The polishing consists of three process, wafer grinding, lapping and chemical mechanical polishing (CMP), which are completed in shortest about 200 minutes in total for 2 inch wafer. Specimens of 4H- and 6H-SiC were provided from slicing single crystal as wafers oriented (0001) with 0 or 8 degrees offset angle toward to <112 _ 0>. By the first grinding using a diamond whetstone wheel, we realized flat surface on the wafers with small TTV error of 1 μm in 15 minutes. After second process of lapping, the wafers were finished by CMP using colloidal silica slurry. AFM observation showed not only scratch-free surface but also atomic steps on the wafers after CMP. Rms marks extremely flat value of 0.08 nm in 10 μm square area.

Abstract: We investigated how surface roughness, intentionally induced by chemical-mechanical polishing, affects the formation of ohmic contacts to an n-type 4H-SiC using a common circular transmission length method (CTLM). Nickel metal was used as the cathode ohmic contacts to n-type SiC. The specific contact resistance (SCR) for the un-polished sample (F1) and polished samples (F2 and F3) was 5.4 × 10-3
⋅cm2 and 4.2 × 10-3
⋅cm2, respectively. We found out that the un-polished sample (F1) had much higher SCR than the samples , F2 and F3. In addition, we did not see any difference between the differently polished samples, F2 and F3, indicating that there was no dependence on the face type of SiC (Si- or C-face) in the values of SCR. We also investigated the die-bonding processes with the surface roughness and metallization schemes' effects.

Abstract: Fast homoepitaxial growth of 4H-SiC has been carried out on off-axis (0001) substrates by horizontal hot-wall CVD at 1600οC. High growth rate up to 24 μm/h has been achieved with mirror-like surface in the C/Si ratio range of 1.0-2.0. The Z1/2 and EH6/7 concentrations can be kept as low as 7 × 1011 cm-3 and 3 × 1011 cm-3, although an unknown trap (UT1) is observed with the concentration in the 1011 cm-3 range. The photoluminescence spectra are dominated by strong free exciton peaks, and the L1 peak is not observed. The basal-plane dislocation (BPD) density has decreased with increase in growth rate, and it can be reduced to 22 cm-2 when epilayers are grown on Chemical Mechanically Polished (CMP) substrates at a growth rate of 24 μm/h.

Abstract: The dishing phenomena of soft materials in chemical mechanical polishing (CMP) process were problematic in delineating inlaid metal patterns. The inlaid copper structures were fabricated on Si wafer where SiO2 was thermally grown. Seed layer was deposited by thermal evaporate method followed by copper electrodeposition. Copper was electrodeposited with IBM paddle type electroplating machine to obtain uniform thickness of coating. The dishing amounts were measured at various current density and current type. The dishing amounts with pattern density and line width were also measured. The losses of copper were not sensitively dependent on current density however those were dependent on current type. The dishing amount of copper was decreased at high pattern density especially over 50% and increased with line width. Surface topology and grain size of coating were investigated with surface profilometer and FESEM.