Papers by Keyword: Flash Lamp Annealing

Abstract: One of the main challenging tasks in the prospective technology is the buckling suppression of the 3C-SiC film due to the melting and solidification process and the stress relief as a consequence of the short time Si melting during the Flash Lamp Annealing. To overcome this effect and to stabilize a flat surface morphology an alternative i-FlASiC process was developed. This work refers to the influence of the layer stack modifications by doping and meltstop formation by ion implantation on the wafer buckling. The samples were studied by transmission electron microscopy, high resolution x-ray diffraction and infrared ellipsometry. The aim was to optimize the doping and flash lamp annealing conditions in relation to the i-FLASiC layer stack modification.

Abstract: There is a clear and increasing interest in short time thermal processing far below one second, i.e. the lower limit of RTP (Rapid Thermal Processing) called spike annealing. It is the world of processing in the millisecond or nanosecond range. This was driven by the need of suppressing the so-called Transient Enhanced Diffusion in advanced boron-implanted shallow pnjunctions in the front-end silicon chip technology. Meanwhile the interest in flash lamp annealing (FLA) in the millisecond range spread out into other fields related to silicon technology and beyond. This paper reports shortly about the restart in flash lamp annealing of the Rossendorf group in collaboration with the Mattson group and further on recent experiments regarding shallow junction engineering in germanium, annealing of ITO (indium tin oxide) layers on glass and plastic foil to form an conductive layer as well as investigations which we did during the last years in the field of wide band gap semiconductor materials (SiC, ZnO). Moreover recent achievements in the field of silicon-based light emission basing on Metal-Oxide-Semiconductor Light Emitting Devices will be reported. Finally it will be demonstrated that the basic principle of short time thermal processing, i.e. surface heating on a colder bulk, features also advantages regarding the casting of lead sheets to produce organ pipes in the spirit of the 17th century.

Abstract: We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.

Abstract: The recent progress of advanced millisecond annealing (MSA) technology is discussed for the application to the advanced logic LSI fabrication processes. The combination with conventional spike annealing and MSA is proving practical to reduce the parasitic resistance and control the dopant diffusion. The characterization result of advanced 45 nm generation devices including the channel straining technology using embedded SiGe epitaxial growth is described with the arrangements of process flow and annealing steps. MSA has a principle problem of the annealing temperature variation depending on the optical properties of materials on the wafer surface because the annealing process time is similar to the heat transfer time. In the device scale, the variation of temperature is examined as the exact temperature with newly proposed evaluating methods used for the first time in this industry.

Abstract: This paper reports on the ultra-rapid thermal annealing of next generation MOSFETs. In ultra-rapid thermal annealing, the most important issue is to achieve a good balance between electrical activation and impurity diffusion. Another issue of annealing implantation damages is also discussed: Optimized annealing combined with millisecond annealing and conventional halogen lamp annealing is necessary for annealing out defects at end-of range region. Application possibilities of millisecond annealing for deep junction activation and oxidation are also discussed.

Abstract: The epitaxial relationship of Si deposited on 3C-SiC was studied using both free standing 3C-SiC(100) material from Hoya and 3C-SiC thin layers deposited on Si(100) as substrates. The conditions of Si growth were varied depending on the substrate. When Si is deposited at 1000°C on (001) 3C-SiC, it is in perfect epitaxial relation with the SiC layer [100]Si//[100]SiC and [001]Si//[001]SiC. After a 20 ms flash lamp pulse on the same sample, which has the effect of fast melting of the Si top layer only, the defects in the Si are eliminated. Using free standing 3C-SiC, the deposition temperature was not limited by the Si melting point so that it was fixed at 1500°C in order to form a set of Si liquid droplets on the surface with diameters ranging from 5 to 20 μm. Surprisingly more than 60% of the Si droplets exhibit the epitaxial relation [110]Si//[001]SiC and [111]Si//[110]SiC after crystallization. The occurrence of this epitaxial relationship can be understood in terms of lattice mismatch reduction from 20% to 18.3%. The conditions of crystallization, most probably the cooling rate, seem to have a strong effect on Si orientation.

Abstract: Flash lamp annealing of multilayer stack of the type SiC/Silicon overlayer(SOL)/SiC reduces the defect densities in the 3C-SiC/Si heteroepitaxial structure. Ge and C additions to the SOL lead to a substantial increase of the mass transfer from the upper layer to the lower SiC layer. If the Ge content of the SOL and the flash lamp annealing conditions are properly chosen a homogeneous layer with a 3C-SiC thickness between 150 and 200 nm can be achieved corresponding to a growth rate between 7.5 and 10.0 +m/s. The thickening of the lower layer depends on the SOL composition. Ge and/or C incorporation into the SOL and therefore into the Si melt enhances the mass transport from the upper SiC layer to the lower one.

Abstract: This paper gives an insight into the thermal modeling of the i-FLASiC process, which is the flash lamp annealing of a 3C-SiC and silicon multilayer system. The model uses a standard heat flow model combined with an advanced multilayer optical model. Results from the model are consistent with experimentally observed phenomenon and have been used to explain diffusion mechanisms for the LPE of SiC.

Abstract: Thin 3C-SiC films epitaxially grown on Si-substrate are substantially improved by the FLASIC process, which involves irradiation with flash lamps with pulse duration of 20ms. The disadvantages of the standard FLASIC process are the undulations introduced in the SiC film due to melting of the Si-substrate and the Si mass transport near the SiC/Si interface during the flash. An improved structure was realised in order to minimize the undulations of the SiC, improving also the quality of the film. This structure involves the deposition of a silicon overlayer (SOL) on the initial SiC layer, followed by an additional SiC capping layer acting as a source for SiC transfer by liquid phase epitaxy to the lower SiC layer. Significant mass SiC transport from the upper to the lower SiC layer through the SOL occurs during the flash. The new structure is characterized as inverse - FLASiC. The structural characteristics of the new structure were studied by transmission electron microscopy and atomic force microscopy.