Papers by Keyword: Gate Dielectrics

Abstract: We report on a very low density (<5×10¹¹ cm^-2) of near-interface traps (NITs) at the Al₂O₃/4H-SiC interface estimated from capacitance-voltage (CV) analysis of MOS capacitors at different temperatures. The aluminum oxide (Al₂O₃) is grown by repeated deposition and subsequent low temperature (200°C) oxidation for 5 min of thin (1-2 nm) Al layers using a hot plate. We refer to this simple method as hot plate Al₂O₃. It is observed that the density of NITs is significantly lower in the hot plate Al₂O₃ samples than in samples with Al₂O₃ grown by atomic layer deposition (ALD) at 300°C and in reference samples with thermally grown silicon dioxide grown in O₂ or N₂O ambient.

Abstract: This essay aims to introduce development of gate dielectrics. In present-day society, Si-based MOS has met its physical limitation. Scientists are trying to find a better material to reduce the thickness and dimension of MOS devices. While substrate materials are required to have a higher mobility, gate dielectrics are expected to have high k, low Dit and low leakage current. I conclude dielectrics in both Si-based and Ge-based MOS devices and several measures to improve the properties of these gate dielectric materials. I also introduce studies on process in our group and some achievements we have got. Significantly, this essay points out the special interest in rare-earth oxides functioning as gate dielectrics in recent years and summarizes the advantages and problems should be resolved in future.

Abstract: Effects of the O2/Ar flow ratio in the reactive sputtering process and the annealing temperature on the structure and surface roughness of ZrO2 films and the electric properties of Pt/ZrO2/Si MOS capacitors in which the ZrO2 film was deposited by magnetron sputtering have been investigated. The optimum process parameters of the Pt/ZrO2/Si capacitor based on reactively sputtered- ZrO2 determined in such a way as the capacitance is maximized and the leakage current, the oxide charge, and the interface trap density are minimized is the O2/Ar flow ratio of 1.5 and the annealing temperature of 800°C