Papers by Keyword: Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)

Abstract: In order for SiC-MOSFET to be practical in various power electronics applications, low specific on-resistance Ron,sp, high breakdown voltage and “normally-off” characteristics have to be fulfilled even at high temperature. We fabricated a SiC-MOSFET employing a submicron gate with channel length Lg of 0.5μm by a self-aligned implantation and aδ-doped epitaxial channel layer to successfully demonstrate the following features. The normally-off characteristics was confirmed from room temperature to 200°C where the therethold voltages Vth were 2.9V at room temperature and 1.6V at 200°C, respectively. The Ron,sp were 4.6mΩcm2 at room temperature and 9.2mΩcm2 at 200°C, respectively, while the breakdown voltage was greater than 1400V .

Abstract: Large (3.6 x 3.6 mm2) chips of the SiC DACFET were fabricated and mounted in TO220 packages. The drain-source avalanche breakdown voltage without any gate bias (Vgs=0V) is measured to be >1400V. The SiC DACFET keeps the normally-off characteristics even at 150°C. Ron and specific Ron of the SiC DACFET is measured to be 62mΩ and 6.7 mΩcm2 at RT while those at 150°C change to 107 mΩ and 11.6 mΩcm2. The 400V / 3 kW DC-DC switched-mode power-conversion circuit with 100kHz switching was fabricated using the SiC DACFET and the SiC SBD. The turn-off switching loss reduces dramatically using the SiC-DACFET down to 77μJ/pulse which is less than 1/10 of that using the Si-IGBT.

Abstract: Today a main focus in high efficiency power electronics based on silicon carbide (SiC) lies on the development of an unipolar SiC switch. This paper comments on the advantages of SiC switching devices in comparison to silicon (Si) switches, the decision for the SiC JFET against the SiC MOSFET, and will show new experimental results on SiC JFETs with focus on the production related topics like process window and parameter homogeneity which can be achieved with the presented device concept. Due to material properties unipolar SiC switches have, other than their Si high voltage counterparts, very low gate charge, good body diode performance, and reduced switching losses because of the potential of lower in- and output capacitances. The most common unipolar switch is the MOSFET. However, the big challenge in the case of a SiC MOSFET is the gate oxide. A gate oxide on SiC that provides adequate performance and reliability is missing until now. An alternative unipolar switching device is a normally-on JFET. The normally-on behavior is a benefit for current driven applications. If a normally-off behavior is necessary the JFET can be used together with a low voltage Si MOSFET in a cascode arrangement. Recently manufactured SiC JFETs show results in very good accordance to device simulation and demonstrate the possibility to fabricate a SiC JFET within a mass production. A growing market opportunity for such a SiC switch becomes visible.

Abstract: In this paper, we review the state of the art of SiC switches and the technical issues which remain. Specifically, we will review the progress and remaining challenges associated with SiC power MOSFETs and BJTs. The most difficult issue when fabricating MOSFETs has been an excessive variation in threshold voltage from batch to batch. This difficulty arises due to the fact that the threshold voltage is determined by the difference between two large numbers, namely, a large fixed oxide charge and a large negative charge in the interface traps. There may also be some significant charge captured in the bulk traps in SiC and SiO2. The effect of recombination-induced stacking faults (SFs) on majority carrier mobility has been confirmed with 10 kV Merged PN Schottky (MPS) diodes and MOSFETs. The same SFs have been found to be responsible for degradation of BJTs.

Abstract: It was experimentally shown that an ONO gate dielectric carefully formed on 4H-SiC has extremely high reliability even under a negative electric field at least up to a junction temperature of 300°C, making it promising for power MOS and CMOS applications. Medium charge to failure of –30 C/cm2 was achieved for fully processed polycrystalline Si gate MONOS capacitors with an equivalent SiO2 thickness of teq = 44 nm and a 200-μm diameter. The medium time to failure of these capacitors projected for –3 MV/cm exceeds 86 and 6.3 thousand years at room temperature and 300°C, respectively. A parasitic memory action did not appear even when Eox of -6.6 MV/cm was applied for 5000 seconds.

Abstract: We report on the reliability of the gate oxide on C-face of 4H-SiC. Constant current stress TDDB measurement shows that QBD of the gate oxide of f200 [μm] on C-face is as much as 18 [C/ cm2], which is much larger than the typical value (0.1[C/ cm2]) of that on Si-face of 4H-SiC. The lifetimes of the gate oxide under the electric field of 3[MV/cm] are roughly evaluated from the leakage characteristics and obtained QBD. The estimated lifetimes of the gate oxide of f600 [μm] are about 900 years. TDDB measurements of MOSs on two wafers, which have different dislocation densities, show that reliability of gate oxide on C-face is insensitive to the dislocation density. Meanwhile, reliability of the gate oxide is sensitive to the surface defect density: it is significantly degraded on the wafer, which has 2000 surface defects in a whole 2-inch wafer.

Abstract: We have analyzed the effect of post-oxidation nitride anneals (usually with either NO or N2O gases) on SiC MOSFETs. Two 4H:SiC wafers were identically prepared except that one wafer had a nitridation anneal after the gate oxide was formed, while the other was tested as-oxidized. We compared the two processes by making measurements on lateral MOSFETs and MOS capacitors using ID-VGS, C-V, and charge pumping. There was no change in either flatband voltage or interface trap density near the valence band, suggesting that the net fixed charge remained constant (within a few 1011cm-2). However, there was a large shift in the threshold voltage which, when combined with the C-V results, indicates a strong reduction of interface traps near the conduction band of roughly 6.0x1012cm-2 by using the nitridation process. The charge pumping measurements also showed a strong reduction of interface traps. Charge pumping measured a trapping density of 2.5x1012cm-2 for the as-oxidized samples and 5.3x1011cm-2 for the nitrided samples. The frequency-dependence of the charge pumping signal also indicates a spatial distribution of traps, with volumetric trap densities of roughly 1.3x1019cm-3 over 25Å on as-oxidized and 3.8x1018cm-3 over 19Å for nitrided.

Abstract: We apply electrically detected magnetic resonance (EDMR) to variously processed 4H SiC MOSFETs from two vendors. Although, the EDMR line shapes observed are nearly the same for vendor 1 devices subjected to a nitric oxide (NO) anneal and devices without it, the relationship between EDMR and gate voltage differs greatly between these samples. Furthermore, the EDMR response versus gate bias varies dramatically. EDMR results from a third device produced by a second vendor are very different from those provided by the first vendor. This result implies that significantly different defect populations are present in devices fabricated by different vendors.

Abstract: N-channel MOSFETs are irradiated with gamma-rays (g-rays) up to 3.16 MGy(SiO2) at room temperature. Above 1 MGy, the effective channel mobility increases with increasing absorbed dose. A similar increase is observed for the Hall mobility in the inversion layer. In addition, the Hall-effect measurements indicate a reduction of the interface trap density.

Abstract: We report investigations on the fabrication and electrical characterization in the range 27°C -290 °C of normally off 4H-SiC circular MOSFET devices manufactured on p-type semiconductor. An high quality SiO2/SiC interface is obtained by nitrogen ion implantation conducted before the thermal oxidation of SiC. Two samples with different nitrogen concentration at the SiO2/SiC interface and one un-implanted have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. With increasing temperature, in all the samples the threshold voltage decreases and the electron channel mobility increases, reaching the maximum value of about 40 cm2/Vs at 290 °C for the sample with the highest N concentration. The observed improvement of the mobility is related to the beneficial effect of the N presence at the SiO2/SiC interface, which leads to the reduction of the interface trap density with energy close to the conduction band. Our results demonstrate that N implantation can effectively be used to improve the electrical performance of surface n-channel 4H-SiC MOSFETs.