Papers by Keyword: Planarization

Abstract: Chemical Mechanical Polishing(CMP) is currently the most effective planarization method used in the semiconductor industry. Because of the continuous improvement of the wafer size and line width, the CMP process must be promoted and improved. Many studies have been undertaken to try and achieve both a high material remval rate (MRR) while maintaing a high surface quality of silicon wafer, however up until this point it appears that the two objectives are mutually exclusive. In this paper, an innovative method which integrated ultrasonic vibration assisted machining and CMP (UCMP) has been developed. With the use of ultrasonic vibration, the CMP efficiency and the quality of ploished suface improves considerably as shown in this paper. The basic principle effects of ultrasonic vibration are further illustrated and the experiments had been done to demostrate the proper procedure. The results showed that UCMP achieves a higher material removal rate (MRR) and better surface quality at the same time.

Abstract: The size of the photo mask and mother glass used in liquid crystal display production has increased yearly. Large rectangular glass plates are difficult to planarize using rotary-type polishing machines. We have developed a rotary-type polishing machine with tool path control that is optimized by polishing simulation for a rectangular wafer. The present paper describes the planarization of a rectangular plate by simulation. The influence of tool size and the aspect ratio of the rectangular plate on the flatness are clarified. For a square plate, the flatness obtained under optimized oscillation speed is less than a quarter of that obtained under uniform oscillation speed. For rectangular plates with aspect ratios of 1:1.25 and 1:1.5, planarization using a tool having a diameter equal to half the diagonal length of the plate is shown to be difficult because the stock removal distributions in diagonal and short side of the workpiece become the different shape.

Abstract: This paper describes a new fabrication technique for RF MEMS switches where the coplanar waveguide (CPW) is fabricated in a basin. A planar profile and good coverage at the edges in a basin is achieved by spinning and baking the sacrificial positive photoresist (PPR) in multiple steps to fill the basin. The basin structure allows an increase in the length of the membrane resulting in lower pull-in voltage and better isolation. The PPR is removed using Piranha solution (H2SO4:H2O2::3:1). Structures with the gap of about 2.5 µm and the thickness of the gold membrane varying from 1µm to 2.5 µm have been successfully realized.

Abstract: We report a damage-free and efficient planarization process for silicon carbide (SiC) using platinum as a catalyst in hydrofluoric acid (HF) solution. In previous studies, 4H-SiC (0001) on-axis wafers were planarized by this process and an extremely flat surface was obtained. However, electronic device substrates require off-axis wafers. In the present study, 4H-SiC (0001) 8° off-axis Si-face wafers were planarized using a Pt catalyst plate and HF solution. In the first trial using these wafers, the surface roughness worsened and a diagonal pattern was observed by phase-shift interference microscopy. The pattern seemed to have been formed when the Pt plate morphology was transcribed onto the wafer. The removal rate of the 8° off-axis Si-face wafer is much greater than that of the on-axis Si-face wafer. Thus, we concluded that the use of a smoother catalyst plate would be necessary to obtain a smooth 8° off-axis Si-face wafer surface. Improving the Pt plate morphology by hand lapping also improved the surface roughness of the processed wafer as compared with the preprocessed surface. The maximum height of the surface irregularity (peak-to-valley, P-V) and root-mean-square roughness were improved to 0.513 nm and 0.044 nm, respectively, as determined by atomic force microscopy (2×2 μm2).

Abstract: SiO2 is a kind of widely used dielectric material in ULSI and its chemical mechanical planarization (CMP) is one of the most difficult processes. In this paper, the CMP mechanism and the effect of abrasive on SiO2 dielectric were analyzed; the different factors of affecting the CMP were analyzed. A kind of organic alkali was chosen to act as the pH regulator and complexation agent to enhance the chemical effect. The silica sol was selected as abrasive to realize no contamination, low viscidity, proper hardness and easy to clean. The effect of different concentration of abrasive on the removal rate and surface performance were studied. Further more the influence of polishing slurry flow and surfactant on removal rate were analyzed. The final planarization was realized.

Abstract: As copper technology moves from pilot to volume manufacturing, semiconductor fabrication is focused on methods to improve device yield. In especially semiconductor manufacturing, electrochemically deposited copper is the material of choice for advanced interconnect applications. Electrochemical deposition (ECD) employs copper plating electrolytes with organic additives to achieve bottom-up filling of small vias and trench with high aspect-ratios. However, for features with small aspect-ratios, the ECD process yields conformal layers because the additives and the bottom-up fill mechanism are not operative in such large features. So, ECD process does not achieve within-die and within-wafer planarity of the deposited copper layer. For planarization of large features and obtaining globally and locally flat films, an electro-chemical mechanical deposition (ECMD) method has been employed. ECMD process is a novel technique that has ability to deposit planar conductive films on non-planar substrate surfaces. Technique involves simultaneous ECD roles and mechanical sweeping of the substrate surface. Copper layer deposited by the ECMD process grows preferentially in cavities on the wafer surface yielding flat profiles and much reduced overburden thickness. Preferential deposition into the cavities on the substrates surface may be achieved through two different mechanisms. The first mechanism is more mechanical in nature and it involves material removal from the top surface. The second mechanism is more chemical in nature and it involves enhancing deposition into the cavities where mechanical sweeping does not reach, and reducing deposition onto surfaces that are swept. Planar layers obtained by the ECMD technique are suitable for low stress material removal processes. Planar layers also yield improved parametric results in device structures after the material removal step. In this study, we demonstrate mechanical role of pad gives effects in ECMD process. So we evaluate gap-filling and planarization between ECMD and ECD.

Abstract: This paper presents a laser-assisted Cu-CMP (Chemical Mechanical Polishing) method for obtaining higher planarized surface by forming laser aggregation particles on recessed areas of uneven copper surface before polishing. At first, the laser trapping of fine particles in slurry and the formation of aggregated marks on the copper wafer surface were investigated by fundamental experiments based on optical radiation pressure. Next, proposed planarization method for uneven surface of copper wafer was attempted. As the polishing processed, the height of aggregated marks was reduced. Then, it was confirmed that the aggregated marks played a role of masks, and no material removal at the bottom surface of recessed areas took place during polishing. This process made it possible to realize high planarity on copper wafer surface.