Papers by Keyword: Polycrystalline SiC

Abstract: This paper details the characterization of polycrystalline SiC (poly-SiC) thin films deposited by low pressure chemical vapor deposition. Films were deposited on both Si and SiO2- coated Si substrates using dichlorosilane (SiH2Cl2) and acetylene (C2H2) as precursor gases. Low residual tensile stress films were deposited at 900°C at a pressure of 2 Torr using SiH2Cl2 and C2H2 (5% in H2) flow rates of 35 sccm and 180 sccm, respectively. XRD analysis of these films indicated a (111) 3C-SiC orientation regardless of substrate material. Both resistivity (1.3
-cm) and residual stress gradient (17 MPa/μm) were found to be relatively low and decreased as the film thickness increased. Unintentional nitrogen doping is responsible for the low resistivity measurements and its concentration in the films was about 1.86 x 1016 cm-3. Poly-SiC films exhibiting near-zero residual tensile stress, low stress gradient and relatively low resistivity have favorable properties for design and fabrication of MEMS devices.

Abstract: A selective atmospheric pressure chemical vapor deposition (APCVD) process has been developed to deposit porous polycrystalline silicon carbide (poly-SiC) thin films containing a high density of through-pores measuring 50 to 70 nm in diameter. The selective deposition process involves the formation of poly-SiC films on patterned SiO2/polysilicon thin film multilayers using a carbonization-based 3C-SiC growth process. This technique capitalizes on significant differences in the nucleation of poly-SiC on SiO2 and polysilicon surfaces in order to form mechanically-durable, chemically-stable, and well anchored porous structures, thus offering a simple and potentially more versatile alternative to direct electrochemical etching.

Abstract: The transfer by wafer-bonding of single-crystalline SiC thin films to a polycrystalline SiC support to obtain a “quasi-wafer” is an attractive way for lowering the cost of silicon carbide wafers. Such a process needs high quality polycrystalline substrates, with controlled and high-level bulk properties (thermal conductivity, electrical resistivity) and with very low surface roughness and surface bowing. Currently, polycrystalline SiC wafers which are available are siliconized SiC or CVD processed SiC wafers. Siliconized ceramic wafers are very heterogeneous (mixture of 3C, 6H, 15R and silicon), while CVD ones are of better quality (homogeneous and textured 3C). However neither the siliconized SiC nor the CVD SiC can be CMP polished with low roughness over large dimension. In this paper, wafers with large and textured grains (> 1cm) are processed and characterized. The polishing of such structures is studied and optimized to obtain low surface roughness. To meet these requirements high temperature processes used for single crystal growth were selected. Structural investigations performed on the grown ingots showed an important influence of the used seed since no preferential crystallographic orientation was observed during the growth. The final polishing quality was of high level but step heights were observed between grains.