Papers by Keyword: RESURF

Abstract: This paper aims to provide detailed experimental results of 4H-SiC vertical and lateral MOSFETs fabricated on the same 6-inch substrate using a single process flow. The cell optimization and fabrication scheme of both vertical and lateral MOSFETs are described in this paper. The measured electrical characteristics from both structures such as on-resistance, transconductance, threshold voltage, breakdown voltage, and capacitances are discussed. Resistance distribution and figure-of-merits of [R_on×C_iss], [R_on×C_oss], and [R_on×C_rss] for vertical and lateral MOSFETs are compared to further improve the characteristic of the lateral MOSFET.

Abstract: In this work, a lateral 4H-SiC n-LDMOS transistor, based on the principle of a reduced surface field due to charge compensation, is investigated by numerical simulations, in order to find adequate fabrication parameters for a lightly doped p-type epitaxy in combination with a higher doped channel region. The purpose of this work is the integration into an existing technology for a 10 V 4H-SiC-CMOS process. The simulations predict in a blocking voltage of 1.3 kV in combination with an On-resistance of 17 mΩcm² for a device with a RESURF structure with a total implanted Al concentration of 6∙10¹⁶ cm^-3 and a depth of 1 μm, a field plate of 5 μm and a drift region of 20 μm. The threshold voltage varies from 5 V to 10 V, depending on the thickness of the gate oxide (50 nm to 100 nm).

Abstract: A comparable study is made on the energy capability of 190 V LDMOSFETs in Si/SiC, SOI, PSOI and PSOSiC technology, using capacitive and inductive switching circuits established in SILVACO Mixed-mode simulators. The results show that the PSOSiC has a thermal advantage compared with other SOI structures under a 48-μs-power-pulse condition, but the Si/SiC device offers superior cooling and energy handling ability in all switching cases despite having a larger chip area.

Abstract: In this paper, the thermal conductivity of lateral double diffused metal oxide semiconductor (LDMOS) was studied. In order to optimize their properties, the LDMOS device based on the lower surface of field (RESURF) theory join the second field plate technology. Power device self-heating effect will affect the carrier mobility, making its negative resistance effect in IV characteristic curve under the high-power condition. As the thermal conductivity of SiO2 is low, the self-heating effect of SOI device is more obvious. The simulation using Silvaco -TCAD software for different buried oxide (BOX) with different SOI layer thickness accordingly show that the thicker SOI layer and the thinner buried oxide layer, the smaller the self-heating effect.

Abstract: Complementary lateral structures, N-JFETs, P-JFETS and bipolar diodes, have been implemented in p and n-type 4H-SiC wafers with epilayers. The device were optimized using finite element code MEDICITM simulations, based on ion implanted and etched Reduced-Surface-Field structures. Two Ti/Ni alloy composition are found to form ohmic contacts compatibles with high temperature device operation. 900°C and respectively 1000°C post-metallisation annealing during 2min are necessary. The presence of a graphite layer is determined by XPS (X-ray photon spectroscopy) analyses at the metal-semiconductor interface. On the fabricated p and n-type lateral JFETs, in blocking state, breakdown voltage as high as 600V are obtained.

Abstract: We fabricated a multi-chip module of 4H-SiC reduced surface field (RESURF)-type lateral JFETs. A single chip consists of 4 unit devices of 2.0 mm × 0.5 mm in size, which were isolated electrically from each other. The multi-chip module consists of 8 chips mounted on an AMC substrate. The drain current and the breakdown voltage of the module are over 3 A and 771 V, respectively. The turn-on time and the turn-off time are 36ns and 166ns, respectively. The module resistance is proportional to the absolute temperature to the 1.05th power.

Abstract: 4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.

Abstract: Optimum dose designing for 4H-SiC (0001) two-zone RESURF MOSFETs is investigated by device simulation and fabrication. Simulated results suggest that negative charge at the SiC/SiO2 interface significantly influences breakdown voltage. Simulation has also showed that breakdown voltage strongly depends on LDD (Lightly-Doped Drain) dose. The dose dependencies of the breakdown voltage experimentally obtained are in good agreement with the device simulation. A RESURF MOSFET, processed by N2O oxidation, with an optimized dose blocks 1080V and has a low on-resistance of 79 mcm2 at a gate oxide field of 3.0 MV/cm, which is the best 4H-SiC RESURF MOSFET ever reported.