A Hybrid NoC-Based MPSoC Simulator

Lin Xiang Shi; Zhe Zhang

doi:10.4028/www.scientific.net/AEF.6-7.238

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HomeAdvanced Engineering ForumAdvanced Engineering Forum Vols. 6-7A Hybrid NoC-Based MPSoC Simulator

A Hybrid NoC-Based MPSoC Simulator

Abstract:

A hybrid MPSoC (Multi-Processor SoC) simulator was proposed in this paper. The simulator provides statistical traffic model and behavior-level model for computation, along with cycle-accurate model on basis of ISS (Instruction-Set Simulator) including ARM and TI DSP. The simulator also provides NoC (Network-on-Chip) and traditional bus for on-chip communication and interconnection. As shown in the case study, the proposed simulator may improve the efficiency of building-up a multi-core simulation platform, and then may be used for simulation and evaluation of the constructed multi-core and NoC architectures.

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Periodical:

Advanced Engineering Forum (Volumes 6-7)

Pages:

238-242

DOI:

https://doi.org/10.4028/www.scientific.net/AEF.6-7.238

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Online since:

September 2012

Authors:

Lin Xiang Shi, Zhe Zhang

Keywords:

BUS, Instruction-Set Simulator, Network-on-Chip (NoC)

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Creative Commons CC BY 4.0

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References

[1] Benini L., De Micheli G. Networks on Chips: A New SoC Paradigm[J]. IEEE Computers, 2002, V35(1): 70-78.

DOI: 10.1109/2.976921

Google Scholar

[2] LS Peh, WJ Dally. A Delay Model and Speculative Architecture for Pipelined Routers[C]. International Symposium on High-Performance Computer Architecture(HPCA), Nuevo Leone, Mexico, 2001: 255-266.

DOI: 10.1109/hpca.2001.903268

Google Scholar

[3] TM Parks. Bounded Scheduling of Process Networks[D]. University of California, (1995).

Google Scholar

[4] T. Kangas. Methods and Implementation for Automated System on Chip Arcihtecture Exploration[EB/OL]. http: /www. martes-itea. org/public/papers/Kangas_-_Methods_and_Implementatio. pdf.

Google Scholar