Error Recovery System Encoder/Decoder Method and VHDL Design for Saving Memory of Embedded System

Byung Joon Kim; Rae Cho Sung; Sung Ho Jin

doi:10.4028/www.scientific.net/AMM.110-116.4985

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 110-116Error Recovery System Encoder/Decoder Method and...

Error Recovery System Encoder/Decoder Method and VHDL Design for Saving Memory of Embedded System

Abstract:

Unexpected errors may occur in any embedded systems. An error correction circuitry is used to prevent system errors. Parity bits generated from an encoder are needed to perform an error recovery process. Therefore, to be stored in the memory space should be added. In this paper, Parity bits to be stored without a memory space that can be used to error correction circuitry are proposed. The proposed method was designed in VHDL. The proposed design used the Reed-Solomon (RS) code of an error correction method. Then, 8 bits of information symbols and a symbol error correcting RS code were designed based on the design.

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Periodical:

Applied Mechanics and Materials (Volumes 110-116)

Pages:

4985-4991

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.110-116.4985

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Online since:

October 2011

Authors:

Byung Joon Kim, Rae Cho Sung, Sung Ho Jin

Keywords:

Decoder, Encoder, Error Reocvery Code, Information Symbol, Parity Symbol, Reed-Solomon Code

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