Simulation results illustrate that there is an optimum-energy supply voltage point (Vopt) for SoC. And these voltage points normally lie in weak sub-threshold or near-threshold region. Considering about the degraded robustness under this low supply voltage, structural change instead of the sizing change is considered in proposed design. Different from conventional 6T SRAM design, the trip point voltage of proposed design changes according to bit-line voltage values. In this way, its read margin is 45% greater than conventional 6T SRAM. The proposed bit-cell exhibits wide hysteresis effect, making the design less vulnerable to process variation. Its hold margin is 30.2% greater than conventional 6T SRAM. The optimum-energy supply voltage of proposed array (256×16) is 400 mV. At the same time, the power consumption at 400 mV decreases to 16% compared to that at 1200 mV.