A Design of VB-DDC Using DA-Based Systolic FIR Filter

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In this paper, we present yet another design of the variable-bandwidth digital down-converter (VB-DDC). The shaping filter in the DDC architecture is substitute with a method which is implemented with fully pipelined computing structure of systolic decomposition for distributed arithmetic (DA) based FIR filer. The systolic structure of the FIR filter involves significantly less memory and complexity compared with the existing ones. The effectiveness of the design is validated by the proposed FPGA implementation results.

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3950-3953

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October 2011

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© 2012 Trans Tech Publications Ltd. All Rights Reserved

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[1] Marrhew T. Hunter, Wasfy B. Mikhael and Achilleas G. Kourtellis: Wideband Digital Downconverters for Synthetic Instrumentation, IEEE Trans. On Instrumentation and Measurement, vol. 58, No. 2, pp.263-269, Feb. (2009).

DOI: 10.1109/tim.2008.2005968

Google Scholar

[2] R. Mahesh and A. P. Vinod: Reconfigurable Frequency Response Masking Filters for Software Radio Channelization, IEEE Trans. On Circuits and Systems-II: Express Briefs, vol. 55, No. 3, pp.274-278, March (2008).

DOI: 10.1109/tcsii.2008.918996

Google Scholar

[3] S. A. White: Applications of distributed arithmetic to digital signal processing: A tutorial review, IEEE Acoust. Speech Signal Processing Mag., vol. 6, pp.4-19, July (1989).

DOI: 10.1109/53.29648

Google Scholar

[4] Kyung-Saeng Kim and Kwyro Lee: Low-power and area efficient FIR filter implementation suitable for multiple taps, IEEE Trans. On VLSI systems, vol. 11, No. 1, pp.150-153, Feb. (2003).

DOI: 10.1109/tvlsi.2002.801570

Google Scholar

[5] P. K. Meher: Hardware-efficient systolization of DA-based calculation of finite digital convolution, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 8, pp.707-711, Aug. (2006).

DOI: 10.1109/tcsii.2006.877277

Google Scholar

[6] P. K. Meher, Shrutisagar Chandrasekaran and Abbes Amira: FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic, IEEE Trans. On Signal Processing, vol. 56, no. 7, pp.3009-3017, Jul. (2008).

DOI: 10.1109/tsp.2007.914926

Google Scholar

[7] Wang Xiao, Xia Wei, Han Chun Lin: An FPGA implementation of variable-bandwidth digital down-converter in wideband digital receiver, in Application of Electronic Technique. 2010(7).

Google Scholar

[8] FIR Compiler User Guide, http: /www. altera. com/literature.

Google Scholar