Online Test Technology for Reversible Circuits

Jing Hu; Dian Zhong Wen

doi:10.4028/www.scientific.net/AMM.160.337

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 160Online Test Technology for Reversible Circuits

Online Test Technology for Reversible Circuits

Abstract:

A new technique is presented for online test with some garbage lines in reversible circuits. Firstly, testable structures for reversible logic are given. Then, a scan-D Flip-Flops for constructing scan-chains is provided. Using the new scan-D Flip-Flops, test programs for reversible circuits were analyzed. The proposed method was tested on a set of reversible benchmarks. It realized online test.

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Periodical:

Applied Mechanics and Materials (Volume 160)

Pages:

337-340

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.160.337

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Online since:

March 2012

Authors:

Jing Hu, Dian Zhong Wen

Keywords:

Design-for-Test (DFT), Online Test, Reversible Circuits

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References

[1] Li Zhiqing, Chen Hanwu, Xu Baowen: A fast algorithm for synthesis of quantum reversible logic circuits, Chinese Journal of Computers, 32, 7, (2009), pp.1291-1303.

DOI: 10.3724/sp.j.1016.2009.01291

Google Scholar

[2] Zilic Z, Radecka K, Kazamiphur A: Reversible circuit technology mapping from non-reversible specifications, Proceedings of the conference on Design, Automation and Test in Europe, Los Alamitos: IEEE Computer Society Press(2007), pp.558-563.

DOI: 10.1109/date.2007.364652

Google Scholar

[3] Patel K N, Hayes J P, Markov I L: Fault testing for reversible circuits, IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems, 23( 2004), pp.1220-1230.

DOI: 10.1109/tcad.2004.831576

Google Scholar

[4] Xiao Fangying, Chen Hanwu: Fault localization for broken control in quantum circuits, Journal of Computer Research and Development, 46, 2(2009), pp.321-328.

Google Scholar

[5] Rahman H, Kole D K, Das D K: Detection of bridging faults in reversible circuits, The IUP Journal of Computer (2010), pp.384-392.

Google Scholar

[6] Bubna M, Goyal N, Sengupta I: A DFT methodology for detecting bridging faults in reversible logic circuits, Proceedings of IEEE Region 10 Conference, Los Alamitos: IEEE Computer Society Press(2007). pp.1-4.

DOI: 10.1109/tencon.2007.4428915

Google Scholar

[7] Polian I, Fiehn T, Becker B: A family of logical fault models for reversible circuits, Proceedings of 14th Asian Test Symposium, Los Alamitos: IEEE Computer Society Press(2005), pp.422-427.

DOI: 10.1109/ats.2005.9

Google Scholar

[8] Vasudevan D P, Lala P K, Di J: Reversible-logic design with online testability, IEEE Transactions on Instrumentation and Measurement, 55, 2(2006), pp.406-414.

DOI: 10.1109/tim.2006.870319

Google Scholar