Design of High-Speed Decoder for New High-Speed Bus

Abstract:

This paper presents a new type of high-speed error correction for the requirements of new high-Speed Bus. Use RS (255, 239). Not only optimization traditional algorithm, but also design bidirectional synchronous calculated adjoint form module, Fast B-M algorithm module. and full parallel Chien Search module. These design used in new high-Speed Bus, Larger than usual decoder designed to significantly shorten the critical path decoding, and achieve continuous decoding. In addition, this error correction system separated error detection and correction module modules, And after error detection module add intelligent control, which reduced the complexity and power consumption of equipment. The error correction system design for the requirements of the new bus which speed is above 400m / s.

• Periodical: Applied Mechanics and Materials (Volumes 20-23)
• Pages: 958-962
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.20-23.958
• Online since: January 2010
• Authors: Wei Gong Zhang, Bo Yang, Rui Ding, Yong Qin Hu
• Keywords: BM Algorithm, Decoder, Dynamic Reconfiguration, High Speed Decoding, Reed-Solomon

References

[1] Lee Hanho. High-speed VLSI architecture for parallel Reed-Solomon decoder [J]. IEEE Transactions on Very large Scale Integration(VLSI) Systems, 2003, 11(4): 288-294.

DOI: 10.1109/tvlsi.2003.810782

[2] Lee Hanho. An area-efficient Euclidean algorithm block for Reed-Solomon decoder [C]/Proc of IEEE Computer Society Annual Symposium on VLSI. Tampa, FL, 2003: 209-210.

DOI: 10.1109/isvlsi.2003.1183468

[3] Song L, Parhi K K. Systematic design of original and modified Mastrovito multipliers over finite fields of IEEE ISCAS. Orlando, FL, 1999: 508-512.

DOI: 10.1109/iscas.1999.777940

[4] Zhang T, Parhi K K. Systematic design of original and modified Mastrovito multipliers for general irreducible polynomials[J]. IEEE Trans on Computers, 2001, 50(7): 734-749.

DOI: 10.1109/12.936239

[5] Hu Qingsheng, Wang Zhigong, Zhang Jun, et al. Low complexity parallel Chien search architecture for RS decoder[C ]/Proc of IEEE ISCAS. Kobe, Japan, 2005: 340-343.

DOI: 10.1109/iscas.2005.1464594

[6] Zhu Haikun, Shen Bo, Zhang Qianling. Design of a high performance Reed-Solomon decoder with switch box con-trol logic [C]/Proc of the 4th International Conference on ASIC. Shanghai, China, 2001: 452一455.

DOI: 10.1109/icasic.2001.982598

[7] Chen Yanni, Parhi K K. Small area parallel Chien search architectures for long BCH codes [ J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2004, 12(5): 545-549.

DOI: 10.1109/tvlsi.2004.826203

[8] Paar C. Optimized arithmetic for Reed-Solomon encoders[C]/Proc of lEEE International Symposium on Information Theory. Ulm, Germany, 1997: 250-255.

DOI: 10.1109/isit.1997.613165