Poly Gate Proximity Effect Modeling for 40nm CMOS

Abstract:

A new compact and scalable psp model for the layout proximity effect of poly gate in 40nm CMOSFET is proposed. This model takes into account the impact of gate space and neighboring gates number on mobility and flatband voltage. With the silicon verification, saturation current change up to 5%–7% and flatband voltage change up to 6-8mv is modeled in the constructed model. Vthlin, Idlin and Gmmax are also monitored. These good results show the importance of the new model for circuit design in advanced CMOS node.

• Periodical: Applied Mechanics and Materials (Volumes 236-237)
• Pages: 134-138
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.236-237.134
• Online since: November 2012
• Authors: Xi Li, Zheng Ren, Ming Juan Wang, Hui Zhou, Li Jie Sun, Shao Jian Hu, Yan Ling Shi
• Keywords: 40nm, CMOS, Layout, Poly Gate, Spice Model

References

[1] Y. Cao: MOSFET Modeling for 45nm and beyond, IEEE ACM international conference on Computer-aided design, Proceedings of the 2007 IEEE, pp.638-643.

DOI: 10.1109/iccad.2007.4397337

[2] Ke-Wei Su, Yi-Ming Sheu, Chung-Kai Lin, et al.: A Scaleable Model for STI Mechanical Stress effect on Layout Dependence of MOS Electrical Characteristics, Custom Integrated Circuits Conference (2003), pp.245-248.

DOI: 10.1109/cicc.2003.1249396

[3] Y.M. Sheu, K. W. Su, S.J. Yang, et al.: Modeling the Well-Edge Proximity Effect in Highly Scaled MOSFETs, IEEE Custom Integrated Circuits Conference (2005), p.831–834.

DOI: 10.1109/cicc.2005.1568798

[4] C. M. Hu, et al., in: BSIM4. 3. 0 MOSFET Model- User's Manual (2003).

[5] X. Li, W. Wu, and D.B.M. Klaassen, in: PSP 102. 3(2008).

[6] Liebmann R, Nawaz N, Bach K H, et al.: Efficient 2D approximation for Layout-dependence Relaxation of Etch Stop Liner Stress due to Contact Holes, SISPAD (2006), pp.173-175.

DOI: 10.1109/sispad.2006.282866

[7] E. Morifuji, H. Aikawa and H. Yoshimura, et al.: Layout Dependence Modeling for 45-nm CMOS with Stress-Enhanced Technique, Vol. 56, No. 9 (2009), p.1991 – (1998).

DOI: 10.1109/ted.2009.2026121

[8] H. Aikawa, E. Morifuji,T. Sanuki T, et al.: Variability aware modeling and characterization in standard cell in 45 nm CMOS with stress enhancement technique, IEEE VLSI, 2008, pp.90-91.

DOI: 10.1109/vlsit.2008.4588574

[9] H. Tsuno,H. Anzai, M. Matsumura, et al.: Advanced analysis and modeling of MOSFET characteristic fluctuation caused by layout variation, IEEE VLSI, 2007, pp.204-205.

DOI: 10.1109/vlsit.2007.4339693

[10] A.J. Scholten, G.D.J. Smit, and B.A. De Vries, et. al: The New CMC Standard Compact MOS Model PSP: advantages for RF applications, Solid-State Circuits, Vol. 44, Issue 5(2009), pp.1415-1424.

DOI: 10.1109/jssc.2009.2015821

[11] A. Lachtefeld and D.A. Antoniadis: Invertigating the Relationship between Electron Mobility and Velocity in Deeply Scaled NMOS via Mechanical Stress, IEEE  Electron Device Letters , Vol. 22, No. 12(2001), pp.591-593.

DOI: 10.1109/55.974587

[12] H. Park K.S. Jones J.A. Slinkmnn and M.E. Law, 'The Effects of Strain on Dopant Diffusion in Silicon, IEEE IEDM 1993, pp.303-306.