FPGA Implementation of NAND Flash Wear-Levelling Algorithm

Ju Hong Wen; Wei Jiang Wang; Wei Gao; Xiao Nan Fan

doi:10.4028/www.scientific.net/AMM.241-244.1209

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 241-244FPGA Implementation of NAND Flash Wear-Levelling...

FPGA Implementation of NAND Flash Wear-Levelling Algorithm

Abstract:

NAND flash would generate invalid blocks during its manufacturing and using, and the invalid block management is a key point of NAND flash. By studying the structure and storage rules of NAND flash, this paper put forward a wear-levelling algorithm against the invalid blocks of NAND flash based on FPGA. This algorithm use invalid block table and logical-physical address mapping table to manage the invalid blocks and do wear-levelling. The design is implemented by VHDL, and successfully realized the wear-levelling and the reading and writing operations of NAND flash.