Automatic Variable K Module Design of Digital Phase-Locked Loop

Yan Peng Sun; Xia Yu Yang

doi:10.4028/www.scientific.net/AMM.263-266.20

Paper Titles

Preface and Conference Organization

The Design of Switched Reluctance Motor Drive System Based on Single Chip Microcontroller and CPLD
p.3

A New 10T SRAM Cell with Improved Read/Write Margin and No Half Select Disturb for Bit-Interleaving Architecture
p.9

Compact LowPass Filter with Wide StopBand Using Non-Uniform Microstrip Resonant Cells
p.15

Automatic Variable K Module Design of Digital Phase-Locked Loop
p.20

Boundary Element Numerical Method for Electric Potential Generated by Oblique Five-Needle Electrodes
p.25

Dynamic Magnetic Force Analysis of the New Low-Power Radial Magnetic Suspension Bearing
p.30

SLF Electromagnetic Fields in Stratified Media
p.35

Design of Broadband GaN HEMT Power Amplifier with Ku Band
p.39

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 263-266Automatic Variable K Module Design of Digital...

Automatic Variable K Module Design of Digital Phase-Locked Loop

Abstract:

PLL lock signal, there is contradictions in the capture time and capture bandwidth, also in the capture bandwidth and high signal-to-noise ratio. The article adopted the method of timely change bandwidth to resolve these conflicts, and used the VHDL to design a auto-change K module to adjust the bandwidth. Simulation results verify the validity of the module in the side of resolving conflicts between capture time and capture bandwidth, and capture bandwidth and high signal-to-noise ratio too.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 263-266)

Pages:

20-24

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.263-266.20

Citation:

Cite this paper

Online since:

December 2012

Authors:

Yan Peng Sun*, Xia Yu Yang

Keywords:

Automatic Variable K Module, Numerically Controlled Oscillator, Phase-Locked Loop

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] Xiaoting Pu, in: Design and analysis of the DPLL,[J] Modern electronic technology 2008(5):170-178 In Chinese

Google Scholar

[2] Jianping Zhang, in: Phase-locked frequency synthesizer, Science Publishing house, 2011.32-33 in Chinese

Google Scholar

[3] Yongming Li, in:Phase-locked loop design, simulation and application, Tsinghua University Press,2010 In Chinese

Google Scholar

[4] Jiali Wang, Lu Su, in:Frequency synthesizer count, Xi'an University of Electronic Science and Technology Press, 2009 In Chinese

Google Scholar

[5] Hongxia Ni, Xinchang Yang, in: All-digital phase-locked loop in VHDL-based design, Changchun Institute of Technology, 2011 (3) :53-56 In Chinese

Google Scholar

[6] Xiaodong Li:Broadband digital phase-locked loop design and FPGA-based implementation [J]. Electronic Measurement Technology, 2009 (5) :103-106 In Chinese

Google Scholar