The Design of Controller in AVS Video Decoder Chip Based on Openrisc

Abstract:

Separate software is hard to achieve real-time HD decoding for its sequential execution, while pure hardware is unable to complete the complex AVS video decoding. Aiming at this, this paper adopts the SoC scheme to develop the controller in AVS decoder. The author selected the OpenRISC1200 processor for its no licensing fees and completely open source. For AVS decoder’s high-complexity, we reconfigured the core to optimize it and designed some peripherals - SDRAM controller, VGA controller, and Wishbone bus module. By elaborating the module’s design, simulation, synthesis, static timing analysis and formal verification, this paper proposes a solution of high-speed & high integration controller in AVS-SoC decoder chip. This controller can quickly complete the AVS stream parsing and system controlling, and also it can improve the AVS chip’s integration and the versatility. Overall, it has great application value and broad market prospects.

• Periodical: Applied Mechanics and Materials (Volumes 263-266)
• Pages: 53-59
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.263-266.53
• Online since: December 2012
• Authors: Qian Lv*, Jin Lan Zhang
• Keywords: AVS Video Decoder, Controller, OpenRISC1200

References

[1] Jili Ni, Xi Chen and Hui Li, in: CPU source code analysis & chip design and Linux transplant in Chinese, Beijing, Electronic Industry Press(2007).

[2] Information on http://opencores.org

[3] Prakash Rashinkar, Peter Paterson, in: System-on-a-chip Verification Methodology and Techniques, USA, Kluwer Academic Publishers.