Voltage-Mode Multi-Valued Schmitt Trigger with Neuron-MOS Transistors

Abstract:

A novel design scheme of multiple-valued Schmitt trigger using neuron-MOS transistors is presented. By controlling the voltages of the multiple-input gates, the neuron-MOS literal circuits with hysteresis characteristics are firstly designed. Then, the transmission switches used to pass quaternary signal are controlled by the outputs of these literal circuits to realize three hysteresis loops of quaternary Schmitt circuit. The benefit of the proposed quaternary Schmitt trigger is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. The three hysteresis loops are fully adjustable by sizing the ratio of capacitive coupling coefficients. The effectiveness of the proposed Schmitt trigger has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology, and the discrepancy of hysteresis values between the simulated and theoretical results is smaller than 6%.

• Periodical: Applied Mechanics and Materials (Volume 273)
• Pages: 310-315
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.273.310
• Online since: January 2013
• Authors: Guo Qiang Hang, Xuan Chang Zhou, Dan Yan Zhang, Yang Yang
• Keywords: Multiple-Valued Logic, Neuron-MOS Transistor, Schmitt Trigger, Voltage-Mode Circuit

References

[1] S. Chen and M. Ker, A new Schmitt trigger circuit in a 0. 13 μm 1/2. 5 V CMOS process to receive 3. 3-V input signals, IEEE Trans on Circuits and Systems-II: Analog and Digital Signal Processing. 52 (2005) 361-365.

DOI: 10.1109/tcsii.2005.850409

[2] F. Yuan, Differential CMOS Schmitt trigger with tunable hysteresis, Analog Integr Circ Sig Process. 62 (2010) 245-248.

DOI: 10.1007/s10470-009-9366-y

[3] X. Wu, P. Wang and Y. Xia, Design of ternary Schmitt triggers based on its sequential characteristics, In: Proc of ISMVL, IEEE Inc., Piscataway, 2002, pp.156-160.

[4] G. Hang, Design of current-mode CMOS multiple-valued Schmitt triggers based on switch-signal theory, ACTA Electronica Sinica. 34 (2006) 924-927.

[5] J. Shen and P. D. Tougaw, Design of symmetric ternary current-mode CMOS Schmitt inverter, International Journal of Electronics. 85 (1998) 477-482.

DOI: 10.1080/002072198134021

[6] K. Ramkumar and K. Nagaraj, A ternary Schmitt trigger, IEEE Trans on Circuits and Systems, 32 (1985) 732-735.

DOI: 10.1109/tcs.1985.1085779

[7] G. Hang and X. Wu, The research on ternary voltage-mode CMOS Schmitt circuits, Research & Progress of Solid State Electronics. 19 (1999) 410-416.

[8] T. Shibata and T. Ohmi, A functional MOS transistor featuring gate-level weighted sum and threshold operations, IEEE Trans on Electron Device. 39 (1992) 1444-1455.

DOI: 10.1109/16.137325

[9] J. Shen, K. Tanno and O. Ishizuka, Down literal circuit with neuron-MOS transistors and its applications, in: Proc of ISMVL, IEEE Inc., Piscataway, 1999, pp.180-185.

DOI: 10.1109/ismvl.1999.779714

[10] G. Hang, A design technique of neuron MOS binary circuits based on multiple-valued logic, Chinese Journal of Semiconductors, 27 (2006) 1316-1320.

[11] Y. Berg. Low voltage semi floating-gate binary to multiple-value and multiple-value to binary converters, in: Proc of ISMVL, IEEE Inc., Piscataway, 2010, pp.79-82.

DOI: 10.1109/ismvl.2010.22