FPGA Implement of Multi-Channel Real-Time Correlation Processing System

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Abstract:

The traditional real-time correlation processing system in FPGA is implemented in parallel mode. It has disadvantages such as high FPGA resource-consuming, low efficiency and poor flexibility. A time-multiplexed processing architecture takes NIOS processor as system controller, connected with preprocessing module, sliding-correlation processor and memories by Avalon data bus. The transmission of large data block out of sliding-correlation processor employs DMA method for its controlling flexibility, the data transmission between computing units and memory units within the processor employs directly memory access to minimum time delay.

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1925-1929

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February 2013

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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[1] XING Hongyan, TANG Juan. Analysis and survey of algorithms for time-delay estimation. Technical Acoustics. Vol. 27, 2008, pp.110-114. (In Chinese).

Google Scholar

[2] LI Xuemei, TAO Ran, WANG Yue. Summary of the Time Delay Estimation. Radar Science and Technology. Vol. 8, 2010, pp.362-370. (In Chinese).

Google Scholar

[3] Yu Min. Research on Long Range Utral Short Baseline System. Harbin Engineering University. 2005, pp.43-44. (In Chinese).

Google Scholar

[4] Liu Li, Hui Junying. An improved three-point-insert time delay estimation algorithm. Applied Acoustics. Vol. 18, 1999, pp.34-38. (In Chinese).

Google Scholar

[5] Altera Corp. FFT MegaCore Function User Guide. (2009).

Google Scholar