Pipelined RISC Processor Design and FPGA Implementation

Li Xin Gao; Hong Shan Zha

doi:10.4028/www.scientific.net/AMM.336-338.1550

Paper Titles

An 8-Bit 1.72-Gsample/s Two Channel TimeInterleaved Analog-to-Digital Converter Based on PCB Circuit Board
p.1525

An Experimental Study on Synchronizing Process of Synchronizer
p.1532

Design of Bluetooth-Based Smart Home Intelligent Controller
p.1540

Based on PQDIF Data of Harmonic Disturbance Source Orientation
p.1545

Pipelined RISC Processor Design and FPGA Implementation
p.1550

Generation and Circuit Implementation of Grid Multi-Scroll Chaotic Attractors
p.1554

AM3359-Based Enterprise Energy Substation Design
p.1558

A Portable Mind Wave Monitor Headband Applied in Intellectual Disabled Children
p.1563

Design Principle and Data Analysis of Clamp Meter
p.1570

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 336-338Pipelined RISC Processor Design and FPGA...

Pipelined RISC Processor Design and FPGA Implementation

Abstract:

This paper presents a pipelined RISC architecture processor. Five-stage pipeline is used to enhance the performance. Test results show that: the design of processor able to accurately perform all instructions, reaching the functional requirements, and greatly improved performance. Finally, implement the pipelined RISC processor in FPGA.