Voltage Scaling for SRAM in 45nm CMOS Process

Jian Ping Hu; Jia Guo Zhu

doi:10.4028/www.scientific.net/AMM.39.253

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 39Voltage Scaling for SRAM in 45nm CMOS Process

Voltage Scaling for SRAM in 45nm CMOS Process

Abstract:

Scaling supply voltage is an efficient approach to achieve low energy. Scaling supply voltage to sub-threshold region can reach minimum energy consumption but only suits for ultra-low operation frequencies. In order to attain more extensive application, scaling supply voltage to medium-voltage region is an attractive approach especially suiting for mid performances. This paper investigates performances of conventional SRAMs in near-threshold and super-threshold regions in terms of energy dissipation and max operating frequency. All circuits are simulated with HSPICE at PTM 45nm CMOS technology by varying supply voltages from 0.4V to 1.1V with 0.1V steps. The simulation results demonstrate that the conventional SRAMs operate on medium-voltage region can not only keep reasonable speed but also reduce greatly energy consumptions.