The Design of High-Speed CMOS Imaging System Based on SOPC Technology

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This paper introduces a design of a high-speed image acquisition system based on Avalon bus which is supported with SOPC technology. Some peripherals embedded in Avalon bus were customized and utilized in this system, such as imaging unit, decoding unit and storage unit, and these improved the speed of the whole imaging system. The data is compressed to three-fourths of the original by the decoding unit. A custom DMA is designed for moving the image data to the two caches of the SDRAM. This approach discards the method that FIFO must be put up in the traditional data acquisition system. And therefore, it reduced the CPU’s task for data moving. At the same time, the image acquisition and the data transmission can complete a parallel job. Finally, the design is worked on the high-speed image acquisition system which is made up of 2K*2K CMOS image sensor. And it improved the image acquisition speed by three ways: data encoding, custom DMA controller and the parallel processing.

Info:

Periodical:

Edited by:

Yuanzhi Wang

Pages:

523-528

DOI:

10.4028/www.scientific.net/AMM.39.523

Citation:

X. H. Yang et al., "The Design of High-Speed CMOS Imaging System Based on SOPC Technology", Applied Mechanics and Materials, Vol. 39, pp. 523-528, 2011

Online since:

November 2010

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Price:

$35.00

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