The Design of High-Speed CMOS Imaging System Based on SOPC Technology

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This paper introduces a design of a high-speed image acquisition system based on Avalon bus which is supported with SOPC technology. Some peripherals embedded in Avalon bus were customized and utilized in this system, such as imaging unit, decoding unit and storage unit, and these improved the speed of the whole imaging system. The data is compressed to three-fourths of the original by the decoding unit. A custom DMA is designed for moving the image data to the two caches of the SDRAM. This approach discards the method that FIFO must be put up in the traditional data acquisition system. And therefore, it reduced the CPU’s task for data moving. At the same time, the image acquisition and the data transmission can complete a parallel job. Finally, the design is worked on the high-speed image acquisition system which is made up of 2K*2K CMOS image sensor. And it improved the image acquisition speed by three ways: data encoding, custom DMA controller and the parallel processing.

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523-528

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November 2010

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© 2011 Trans Tech Publications Ltd. All Rights Reserved

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[1] Ma Sen, Shang Yuanyuan, Research on Embedded Surveillance Platform in Severe Environment, sec, pp.47-52, 2008 Fifth IEEE International Symposium on Embedded Computing, (2008).

DOI: 10.1109/sec.2008.39

Google Scholar

[2] A. Dandalis and V.K. Prasanna, Configuration Compression for FPGA based Embedded Systems FPGA, 2001, February 11-13, 2001, Monterey CA, USA.

DOI: 10.1145/360276.360342

Google Scholar

[3] Ni F L, Jin M H, A highly integrated joint servo system based on FPGA with Nios II processor, Conf. Proc. On Mechatronics and Automation (Luoyang) 973-8, (2006).

DOI: 10.1109/icma.2006.257757

Google Scholar

[4] D. Lewis and Al, The StratixTM Routing and Logic Architecture, FPGA 03, February 23-25, 2003, Monterey, California, USA.

Google Scholar

[5] Tong J G, Anderson I D L, Soft-core processors for embedded systems, Conf. Proc. On Microelectronics (Dhahran) 170-3, (2005).

Google Scholar

[6] Alistair J. Fitch, Alexander Kadyrov, William J. Christmas and Josef Kittler, Fast Robust Correlation, IEEE, (2005).

Google Scholar

[7] F. Ghozzi, P. Nouel, Ph. Marchegay, Acquisition memorisation video systeme excalibur, IEEE Canada, Conference Canadienne en Genie Electrique et Informatique 2003, Montreal, Mai (2003).

DOI: 10.1109/ccece.2003.1226132

Google Scholar

[8] P. Supan, I. Stuppacher and M. Haller. Image Based Shadowing in Real-Time Augmented Teality, In the International Journal of Virtual Reality, vol. 5, no. 3, pp.1-7, September (2007).

DOI: 10.20870/ijvr.2006.5.3.2692

Google Scholar

[9] Robson C W Bousselham, An FPGA based general purpose data acqui-siton controller, IEEE Transactions on Nuclear Science 10 (2092).

DOI: 10.1109/tns.2006.878698

Google Scholar

[10] McMillan and Bishop. Plenoptic Modeling: An Image-Based Rendering System, In Proceedings of ACM SIGGRAPH 95, ACM Press/ACM SIGGRAPH, New York. ACM, pp.39-46.

DOI: 10.1145/218380.218398

Google Scholar