H.264 Decoder SOC Architecture Based on Co-Processor

Abstract:

This paper presents the architecture and implementation of a H.264 decoder SOC system. The SOC system has mixed hardware arithmetic unit and software instruction based on co-processors, which are designed by analyzing the major arithmetic units of H.264 decoder. The co-processor approach can meet certain performance requirement with high scalability, which can be easy for system upgrade and expansion in the future. The verification result shows that the SOC system can speed up H.264 decoding process by saving more than 75% of the decoding time.

• Periodical: Applied Mechanics and Materials (Volumes 401-403)
• Pages: 1879-1884
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.401-403.1879
• Online since: September 2013
• Authors: Zhi Xun Zhang, Juan Wang, Yong Dong Wang
• Keywords: Co-Processor, H.264, SoC

References

[1] Wiegand T, Sullivan G J, etc. Overview of the H. 264/AVC Video Coding Standard, IEEE Transactions on Circuits And Systems for Video Technology, July 2003, Vol. 13, No. 7, 560-576.

DOI: 10.1109/tcsvt.2003.815165

[2] Schaefer R., T. Wiegand and H. Schwarz, The Emerging H. 264/AVC Standard, EBU TECHNICAL REVIEW, January (2003).

[3] Hashimoto T, Kuromaru S, etc. A 90mw MPEG4 Video Codec LSI with the Capability for Core Profile. in Proc. IEEE Solid-State Circuits Conference, Digest of Technical Paper, (2001).

DOI: 10.1109/isscc.2001.912577

[4] Takahashi M, Nishikawa, etc A Scalable MPEG-4 Video Codec Architecture for IMT-2000 Multimedia Applications. in Proc. Int. Symposium on Circuits and Systems (ISCAS 2000), May (2000).

DOI: 10.1109/iscas.2000.856290

[5] Kongetira, P., Aingaran, K., and Olukotun, K. Niagara: A 32-way multithreaded SPARC processor. IEEE Micro 25, 2 (2005), 21–29.

DOI: 10.1109/mm.2005.35

[6] Sinharoy, B., and ET AL. Power5 system microarchitecture. IBM J. Res. Dev. 49, 4/5 (2005), 505–521.

DOI: 10.1147/rd.494.0505

[7] Gschwind, M., and ET AL. Synergistic processing in cell's multicore architecture. IEEE Micro 26, 2 (2006), 10–24.

[8] Kumar, R., and ET AL. Single-ISA heterogeneous multicore architectures: The potential for processor power reduction. MICRO (2003), 81–92.

[9] Hoare, R., Tung, S., and Werger, K. A 64-way simd processing architecture on an fpga. In IASTED International Conference on Parallel and Distributed Computing and Systems, (2003).

[10] Jiri Gaisler, LEON3 GR-XC3S-1500 Template Design, Gaisler Reserch, http: /www. gaisler. com/cms.

[11] W. Hwangbo, J. Kim and C. M. Kyung, A High-Performance 2-D Inverse Transform Architecture for the H. 264/AVC Decoder, Proceedings of IEEE International Symposium on Circuits and Systems, (2007).

DOI: 10.1109/iscas.2007.378827